{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:07Z","timestamp":1749206407782,"version":"3.41.0"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1999,8,1]],"date-time":"1999-08-01T00:00:00Z","timestamp":933465600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1999,8,1]],"date-time":"1999-08-01T00:00:00Z","timestamp":933465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[1999,8]]},"DOI":"10.1023\/a:1008300821561","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T14:41:38Z","timestamp":1040568098000},"page":"173-189","source":"Crossref","is-referenced-by-count":1,"title":["On Design Validation Using Verification Technology"],"prefix":"10.1007","volume":"15","author":[{"given":"Dinos","family":"Moundanos","sequence":"first","affiliation":[]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"240701_CR1","doi-asserted-by":"crossref","unstructured":"Y.V. Hoskote, D. Moundanos, and J.A. Abraham, \u201cAutomatic Extraction of the Control Flow Machine and Application to Evaluating Coverage of Verification Vectors,\u201d Proc. ICCD, 1995, pp. 532\u2013537.","DOI":"10.1109\/ICCD.1995.528919"},{"key":"240701_CR2","doi-asserted-by":"crossref","unstructured":"R. Ho and M. Horowitz, \u201cValidation Coverage Analysis for Complex Digital Designs,\u201d Proc. ICCAD, 1996, pp. 146\u2013151.","DOI":"10.1109\/ICCAD.1996.569537"},{"key":"240701_CR3","doi-asserted-by":"crossref","unstructured":"J. Burch, E. Clarke, K. McMillan, and D. Dill, \u201cSequential Circuit Verification Using Symbolic Model Checking,\u201d Proc. 27th DAC, 1990, pp. 46\u201351.","DOI":"10.1145\/123186.123223"},{"issue":"1","key":"240701_CR4","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1109\/12.656068","volume":"47","author":"D. Moundanos","year":"1998","unstructured":"D. Moundanos, J.A. Abraham, and Y.V. Hoskote, \u201cAbstraction Techniques for Validation Coverage Analysis and Test Generation,\u201d IEEE Transactions on Computers,Vol. 47, No. 1, pp. 2\u201314, 1998.","journal-title":"IEEE Transactions on Computers"},{"key":"240701_CR5","doi-asserted-by":"crossref","unstructured":"R. Ho, C. Yang, M. Horowitz, and D. Dill, \u201cArchitecture Validation for Processors,\u201d Proc. 22nd International Symposium on Computer Architecture, 1995, pp. 404\u2013413.","DOI":"10.1145\/223982.224450"},{"key":"240701_CR6","doi-asserted-by":"crossref","unstructured":"D. Geist, M. Farkas, A. Landver, Y. Lichtenstein, S. Ur, and Y. Wolfsthal, \u201cCoverage-Directed Test Generation Using Symbolic Techniques,\u201d Proc. Formal Methods in CAD, 1996.","DOI":"10.1007\/BFb0031805"},{"key":"240701_CR7","doi-asserted-by":"crossref","unstructured":"M. Pierre, S. Yang, and D. Cassiday, \u201cFunctional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer,\u201d Proc. ICCD, 1992, pp. 430\u2013435.","DOI":"10.1109\/ICCD.1992.276308"},{"key":"240701_CR8","doi-asserted-by":"crossref","unstructured":"S. Devadas, A. Ghosh, and K. Keutzer, \u201cAn Observability-Based Code Coverage Metric for Functional Simulation,\u201d Proc. ICCAD, 1996, pp. 418, 425.","DOI":"10.1109\/ICCAD.1996.569832"},{"key":"240701_CR9","doi-asserted-by":"crossref","unstructured":"K. Cheng and A. Krishnakumar, \u201cAutomatic Functional Test Generation Using the Extended Finite State Machine Model,\u201d Proc. 30th DAC, 1993, pp. 86\u201391.","DOI":"10.1145\/157485.164585"},{"issue":"2","key":"240701_CR10","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1109\/92.386220","volume":"3","author":"A. Chandra","year":"1995","unstructured":"A. Chandra, V. Ivengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal, \u201cAVPGEN-A Test Generator for Architecture Verification,\u201d IEEE Transactions on VLSI Systems, Vol. 3, No. 2, pp. 188\u2013200, 1995.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"240701_CR11","doi-asserted-by":"crossref","unstructured":"K.D. Jones and J.P. Privitera, \u201cThe Automatic Generation of Functional Test Vectors for Rambus Designs,\u201d Proc.DAC, 1996, pp. 415\u2013420.","DOI":"10.1109\/DAC.1996.545612"},{"issue":"12","key":"240701_CR12","doi-asserted-by":"crossref","first-page":"1143","DOI":"10.1016\/0898-1221(85)90102-6","volume":"11","author":"M. Abadir","year":"1985","unstructured":"M. Abadir and H. Reghbati, \u201cFunctional Specification and Testing of Logic Circuits,\u201d Comp. and Math. with Appls., Vol. 11, No. 12, pp. 1143\u20131153, 1985.","journal-title":"Comp. and Math. with Appls."},{"key":"240701_CR13","doi-asserted-by":"crossref","unstructured":"P. Chung, Y. Wang, and I. Hajj, \u201cDiagnosis and Correction of Logic Design Errors in Digital Circuits,\u201d Proc. 30th DAC, 1993, pp. 503\u2013508.","DOI":"10.1145\/157485.165003"},{"key":"240701_CR14","doi-asserted-by":"crossref","unstructured":"S. Kang and S. Szygenda, \u201cDesign Validation: Comparing Theoretical and Empirical Results of Design Error Modeling,\u201d IEEE Design and Test, 1994, pp. 18\u201326.","DOI":"10.1109\/54.262319"},{"key":"240701_CR15","volume-title":"Formal Techniques for Verification of Synchronous Sequential Circuits","author":"Y.V. Hoskote","year":"1995","unstructured":"Y.V. Hoskote, \u201cFormal Techniques for Verification of Synchronous Sequential Circuits,\u201d Ph.D. Dissertation, ECE Dept., UT Austin, 1995."},{"key":"240701_CR16","doi-asserted-by":"crossref","unstructured":"T.M Niermann and J.H. Patel, \u201cHITEC:A Test Generation Package for Sequential Circuits,\u201d Proc. of EDAC, 1991, pp. 214\u2013218.","DOI":"10.1109\/EDAC.1991.206393"},{"key":"240701_CR17","unstructured":"S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, \u201cAQUILA: An Equivalence Verifier for Large Sequential Circuits,\u201d Proc. of Asia-Pacific DAC, 1997."},{"key":"240701_CR18","doi-asserted-by":"crossref","unstructured":"W. Cullyer, \u201cImplementing Safety-Critical Systems: The Viper Microprocessor,\u201d VLSI Specification, Verification and Synthesis, G. Birtwistle and P. Subrahmanyam (Eds.), Kluwer Ac., 1988, pp. 1\u201326.","DOI":"10.1007\/978-1-4613-2007-4_1"},{"key":"240701_CR19","doi-asserted-by":"crossref","unstructured":"D. Saab, Y. Saab, and J.A. Abraham, \u201cCris: A Test Cultivation Program for Sequential VLSI Circuits,\u201d Proc. ICCAD, 1992, pp. 216\u2013219.","DOI":"10.1109\/ICCAD.1992.279372"},{"key":"240701_CR20","doi-asserted-by":"crossref","unstructured":"Jian Shen and J.A. Abraham, \u201cNative Mode Functional Test Generation fot Microprocessors With Application to Self Test and Design Validation,\u201d Proc. ITC, 1998, pp. 990\u2013999.","DOI":"10.1109\/TEST.1998.743296"},{"key":"240701_CR21","doi-asserted-by":"crossref","unstructured":"D. Moundanos, J.A. Abraham, and Y.V. Hoskote, \u201cA Unified Framework for Design Validation and Manufacturing Test,\u201d Proc. ITC, 1996, pp. 875\u2013884.","DOI":"10.1109\/TEST.1996.557149"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/link.springer.com\/content\/pdf\/10.1023\/A:1008300821561.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/link.springer.com\/article\/10.1023\/A:1008300821561\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/link.springer.com\/content\/pdf\/10.1023\/A:1008300821561.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:10:08Z","timestamp":1749204608000},"score":1,"resource":{"primary":{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/link.springer.com\/10.1023\/A:1008300821561"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,8]]},"references-count":21,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1999,8]]}},"alternative-id":["240701"],"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1023\/a:1008300821561","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1999,8]]}}}