{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,16]],"date-time":"2025-07-16T12:26:36Z","timestamp":1752668796039},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/reconfig.2017.8279824","type":"proceedings-article","created":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:32:24Z","timestamp":1517869944000},"page":"1-6","source":"Crossref","is-referenced-by-count":6,"title":["Thorough analysis of PCIe Gen3 communication"],"prefix":"10.1109","author":[{"given":"Hiroki","family":"Nakamura","sequence":"first","affiliation":[]},{"given":"Hirotaka","family":"Takayama","sequence":"additional","affiliation":[]},{"given":"Yoshiki","family":"Yamaguchi","sequence":"additional","affiliation":[]},{"given":"Taisuke","family":"Boku","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"PCI Express 3 0 Mid-Bus Probe Installation and usage manual","year":"2016","key":"ref30"},{"key":"ref10","article-title":"PCI Express for UltraScale Architecture-Based Devices","author":"lawley","year":"2015","journal-title":"Technical Report"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2693714.2693716"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2013.226"},{"key":"ref13","first-page":"377","article-title":"A preliminarily evaluation of peach 3: A switching hub for tightly coupled accelerators","author":"kuhara","year":"2014","journal-title":"Proceedings of the Computer Networking Symposium"},{"key":"ref14","article-title":"Direct gpu\/fpga communication via pci express","author":"bittner","year":"2013","journal-title":"Cluster Computing"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.02.005"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927459"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2815631"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/664\/9\/092017"},{"journal-title":"Technical Report","article-title":"NVIDIA Corporation. NVIDIA NVlink high-speed interconnect: Application performance","year":"2014","key":"ref19"},{"journal-title":"PCI Express 3 0 Interposer with CLKREQ# and SRIS Support","year":"2015","key":"ref28"},{"journal-title":"The Convey HC-2&#x2122; Computer Architectural Overview conv-12-030","year":"2012","key":"ref4"},{"journal-title":"Summit T3&#x2013;8 Analyzer PCI Express Multi- Lane Protocol Analyzer User manual","year":"2016","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2082156.2082172"},{"journal-title":"XILINX Virtex-7 FPGA Gen3 Integrated Block for PCI Express","year":"2017","key":"ref6"},{"journal-title":"PCIe Protocol Analysis Software 8 50 Release notes","year":"2017","key":"ref29"},{"journal-title":"Introduction to the HPP-Heterogeneous Processing Platform A combination of Multi-core GPUs FPGAs and Many-core accelerators","year":"2013","author":"hariri","key":"ref5"},{"journal-title":"LogiCORE IP Product Guide (v4 1)","article-title":"Virtex-7 FPGA Gen3 Integrated Block for PCI Express","year":"2015","key":"ref8"},{"key":"ref7","article-title":"Understanding Performance of PCI Express Systems","author":"lawley","year":"2014","journal-title":"Technical Report"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.75"},{"journal-title":"LogiCORE IP Product Guide (v4 1)","article-title":"UltraScale Architecture Gen3 Integrated Block for PCI Express","year":"2016","key":"ref9"},{"journal-title":"Cray Inc Cray XD 1 Supercomputer","year":"2004","key":"ref1"},{"journal-title":"PCI-SIG PCI Express Base Specification","year":"0","key":"ref20"},{"journal-title":"VC709 Evaluation Board for the Virtex-7 FPGA","year":"2016","key":"ref22"},{"journal-title":"PCI Express Base Specification","year":"2015","key":"ref21"},{"journal-title":"TB-7VX-690T\/980T\/1140T-PCIeXP Hardware Manual","year":"2014","key":"ref24"},{"journal-title":"VCU108 Evaluation Board","year":"2016","key":"ref23"},{"key":"ref26","article-title":"In-System Eye Scan of a PCI Express Link with Vivado IP Integrator and AXI4","author":"bielich","year":"2014","journal-title":"Application Note XAPP 1198 (v1 1)"},{"journal-title":"Virtual Input\/Output v3 0","year":"2017","key":"ref25"}],"event":{"name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2017,12,4]]},"location":"Cancun","end":{"date-parts":[[2017,12,6]]}},"container-title":["2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"https:\/\/linproxy.fan.workers.dev:443\/http\/xplorestaging.ieee.org\/ielx7\/8268902\/8279767\/08279824.pdf?arnumber=8279824","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,3,12]],"date-time":"2018-03-12T21:51:35Z","timestamp":1520891495000},"score":1,"resource":{"primary":{"URL":"https:\/\/linproxy.fan.workers.dev:443\/http\/ieeexplore.ieee.org\/document\/8279824\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":30,"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1109\/reconfig.2017.8279824","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}