{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:52Z","timestamp":1750221292163,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":0,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T00:00:00Z","timestamp":1518652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,2,15]]},"DOI":"10.1145\/3174243.3174966","type":"proceedings-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T16:12:59Z","timestamp":1519402379000},"page":"287-287","update-policy":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["In-Package Domain-Specific ASICs for Intel\u00ae Stratix\u00ae 10 FPGAs"],"prefix":"10.1145","author":[{"given":"Eriko","family":"Nurvitadhi","sequence":"first","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}]},{"given":"Jeff","family":"Cook","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}]},{"given":"Asit","family":"Mishra","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}]},{"given":"Debbie","family":"Marr","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}]},{"given":"Kevin","family":"Nealis","sequence":"additional","affiliation":[{"name":"Intel Corporation, San Jose, CA, USA"}]},{"given":"Philip","family":"Colangelo","sequence":"additional","affiliation":[{"name":"Intel Corporation, San Jose, CA, USA"}]},{"given":"Andrew","family":"Ling","sequence":"additional","affiliation":[{"name":"Intel Corporation, Toronto, Canada"}]},{"given":"Davor","family":"Capalija","sequence":"additional","affiliation":[{"name":"Intel Corporation, Toronto, Canada"}]},{"given":"Utku","family":"Aydonat","sequence":"additional","affiliation":[{"name":"Intel Corporation, Toronto, Canada"}]},{"given":"Sergey","family":"Shumarayev","sequence":"additional","affiliation":[{"name":"Intel Corporation, San Jose, CA, USA"}]},{"given":"Aravind","family":"Dasu","sequence":"additional","affiliation":[{"name":"Intel Corporation, San Jose, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2018,2,15]]},"event":{"name":"FPGA '18: The 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey CALIFORNIA USA","acronym":"FPGA '18"},"container-title":["Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3174243.3174966","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:33Z","timestamp":1750212693000},"score":1,"resource":{"primary":{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3174243.3174966"}},"subtitle":["A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)"],"short-title":[],"issued":{"date-parts":[[2018,2,15]]},"references-count":0,"alternative-id":["10.1145\/3174243.3174966","10.1145\/3174243"],"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1145\/3174243.3174966","relation":{},"subject":[],"published":{"date-parts":[[2018,2,15]]},"assertion":[{"value":"2018-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}