{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:16:22Z","timestamp":1750220182433,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,7,10]],"date-time":"2022-07-10T00:00:00Z","timestamp":1657411200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000923","name":"Australian Research Council","doi-asserted-by":"publisher","award":["DP190103916"],"award-info":[{"award-number":["DP190103916"]}],"id":[{"id":"10.13039\/501100000923","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,7,10]]},"DOI":"10.1145\/3489517.3530491","type":"proceedings-article","created":{"date-parts":[[2022,8,23]],"date-time":"2022-08-23T23:19:29Z","timestamp":1661296769000},"page":"541-546","update-policy":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["FaSe"],"prefix":"10.1145","author":[{"given":"Tuo","family":"Li","sequence":"first","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]}],"member":"320","published-online":{"date-parts":[[2022,8,23]]},"reference":[{"volume-title":"CCS '15","author":"Yossef","key":"e_1_3_2_1_1_1","unstructured":"Yossef Oren et al. 2015. The spy in the sandbox: practical cache attacks in javascript and their implications. In CCS '15."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Dag Arne Osvik Adi Shamir and Eran Tromer. 2006. Cache attacks and countermeasures: the case of aes. In CT-RSA'06 1--20.","DOI":"10.1007\/11605805_1"},{"key":"e_1_3_2_1_3_1","unstructured":"Daniel J Bernstein. 2005. Cache-timing attacks on AES. Technical report."},{"volume-title":"EuroSys '19","author":"Qian","key":"e_1_3_2_1_4_1","unstructured":"Qian Ge et al. 2019. Time protection: the missing os abstraction. In EuroSys '19, 1:1--1:17."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Leonid Domnitser et al. 2012. Non-monopolizable caches: low-complexity mitigation of cache side channel attacks. TACO 8 4 (January 2012).","DOI":"10.1145\/2086696.2086714"},{"key":"e_1_3_2_1_6_1","volume-title":"MICRO '18","author":"Qureshi Moinuddin K.","year":"2018","unstructured":"Moinuddin K. Qureshi. 2018. Ceaser: mitigating conflict-based cache attacks via encrypted-address and remapping. In MICRO '18, 775--787."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Wei Song et al. 2021. Randomized last-level caches are still vulnerable to cache side-channel attacks! but we can fix it. In S&P '21 955--969.","DOI":"10.1109\/SP40001.2021.00050"},{"volume-title":"CCS '13","author":"Zhang Yinqian","key":"e_1_3_2_1_8_1","unstructured":"Yinqian Zhang and Michael K. Reiter. 2013. D\u00fcppel: retrofitting commodity operating systems to mitigate cache side channels in the cloud. In CCS '13."},{"volume-title":"USENIX ATC '18","author":"Oleksii","key":"e_1_3_2_1_9_1","unstructured":"Oleksii Oleksenko et al. 2018. Varys: protecting sgx enclaves from practical side-channel attacks. In USENIX ATC '18, 227--239."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/63404.63407"},{"volume-title":"ISCA '17","author":"Mengjia","key":"e_1_3_2_1_11_1","unstructured":"Mengjia Yan et al. 2017. Secure hierarchy-aware cache replacement policy (sharp): defending against cache-based side channel atacks. In ISCA '17."},{"volume-title":"MICRO '08","author":"Wang Zhenghong","key":"e_1_3_2_1_12_1","unstructured":"Zhenghong Wang and Ruby B. Lee. 2008. A novel cache architecture with enhanced performance and security. In MICRO '08, 83--93."},{"key":"e_1_3_2_1_13_1","volume-title":"USENIX '19","author":"Mario","year":"2019","unstructured":"Mario Werner et al. 2019. Scattercache: thwarting cache attacks via cache set randomization. In USENIX '19. (August 2019), 675--692."},{"volume-title":"USENIX '12","author":"Taesoo","key":"e_1_3_2_1_14_1","unstructured":"Taesoo Kim et al. 2012. STEALTHMEM: system-level protection against cache-based side channel attacks in the cloud. In USENIX '12, 189--204."},{"volume-title":"HPCA '16","author":"Fangfei","key":"e_1_3_2_1_15_1","unstructured":"Fangfei Liu et al. 2016. Catalyst: defeating last-level cache side channel attacks in cloud computing. In HPCA '16, 406--418."},{"key":"e_1_3_2_1_16_1","volume-title":"USENIX '18","author":"Xiaowan","year":"2018","unstructured":"Xiaowan Dong et al. 2018. Shielding software from privileged side-channel attacks. In USENIX '18. (August 2018), 1441--1458."},{"volume-title":"MICRO '19","author":"Thomas","key":"e_1_3_2_1_17_1","unstructured":"Thomas Bourgeat et al. 2019. Mi6: secure enclaves in a speculative out-of-order processor. In MICRO '19, 42--56."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Nils Wistoff et al. 2020. Prevention of microarchitectural covert channels on an open-source 64-bit RISC-V core. CoRR abs\/2005.02193.","DOI":"10.23919\/DATE51398.2021.9474214"},{"key":"e_1_3_2_1_19_1","unstructured":"Tuo Li et al. 2020. SIMF: single-instruction multiple-flush mechanism for processor temporal isolation. (2020). https:\/\/linproxy.fan.workers.dev:443\/https\/arxiv.org\/abs\/2011.10249."},{"key":"e_1_3_2_1_20_1","volume-title":"Dag Arne Osvik, and Adi Shamir","author":"Tromer Eran","year":"2010","unstructured":"Eran Tromer, Dag Arne Osvik, and Adi Shamir. 2010. Efficient cache attacks on aes, and countermeasures. 23, 1."},{"key":"e_1_3_2_1_21_1","unstructured":"Krste Asanovic et al. 2016. The Rocket Chip Generator. Technical report UCB\/EECS-2016-17. EECS Department University of California Berkeley."},{"key":"e_1_3_2_1_22_1","volume-title":"ATEC '96","author":"McVoy Larry","year":"1996","unstructured":"Larry McVoy and Carl Staelin. 1996. Lmbench: portable tools for performance analysis. In ATEC '96, 23--23."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"e_1_3_2_1_24_1","unstructured":"Yuval Yarom. 2016. Mastik: a micro-architectural side-channel toolkit. (2016). https:\/\/linproxy.fan.workers.dev:443\/https\/cs.adelaide.edu.au\/~yval\/Mastik\/Mastik.pdf."}],"event":{"name":"DAC '22: 59th ACM\/IEEE Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"],"location":"San Francisco California","acronym":"DAC '22"},"container-title":["Proceedings of the 59th ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3489517.3530491","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/3489517.3530491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:17Z","timestamp":1750186937000},"score":1,"resource":{"primary":{"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3489517.3530491"}},"subtitle":["fast selective flushing to mitigate contention-based cache timing attacks"],"short-title":[],"issued":{"date-parts":[[2022,7,10]]},"references-count":24,"alternative-id":["10.1145\/3489517.3530491","10.1145\/3489517"],"URL":"https:\/\/linproxy.fan.workers.dev:443\/https\/doi.org\/10.1145\/3489517.3530491","relation":{},"subject":[],"published":{"date-parts":[[2022,7,10]]},"assertion":[{"value":"2022-08-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}