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Miyake, &#x201C;Analysis of submicron double-gated polysilicon MOS thin film transistors,&#x201D; Tech. Dig. 1990 IEDM, pp.399&#x2013;402, 1990."},{"key":"2","unstructured":"[2] A. O. Adan, K. Suzuki, H. Shibayama, and R. Miyake, &#x201C;A half micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load,&#x201D; Tech. Dig. 1990 VLSI Symp., pp.19&#x2013;20, 1990."},{"key":"3","unstructured":"[3] A. Kumar, J. K. O. Sin, C. T. Nguyen, and P. K. Ko, &#x201C;Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors,&#x201D; IEEE Trans. Electron. Dev., vol.45, no.12, pp.2514&#x2013;2520, 1998."},{"key":"4","unstructured":"[4] K. Makihira, K. Nakagawa, and T. Asano, &#x201C;Double-gate poly-Si thin-film transistors fabricated using self-aligned technology,&#x201D; Tech. Dig. 2001 AM-LCD, pp. 243&#x2013;246, 2001."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Zhang, R. Han, J. K. O. Sin, and M. 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Sheu, &#x201C;Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,&#x201D; IEEE Electron Device Lett., vol.31, no.3, pp.216&#x2013;218, 2010.","DOI":"10.1109\/LED.2009.2038177"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J.-W. Han, S.-W. Ryu, D.-H. Kim, and Y.-K. Choi, &#x201C;Polysilicon channel TFT with separated double-gate for Unified RAM (URAM)&mdash;unified function for nonvolatile SONOS flash and high-speed capacitorless 1T-DRAM,&#x201D; IEEE Trans. Electron. Dev., vol.57, no.3, pp.601&#x2013;607, 2010.","DOI":"10.1109\/TED.2009.2038584"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C.-M. Lee and B.-Y. Tsui, &#x201C;A high-performance 30-nm gate-all-around poly-Si nanowire thin-film transistor with NH<SUB>3<\/SUB> plasma treatment,&#x201D; IEEE Electron Device Lett., vol.31, no.7, pp.683&#x2013;685, 2010.","DOI":"10.1109\/LED.2010.2049564"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] H.-H. Hsu, H.-C. Lin, and T.-Y. Huang, &#x201C;Origins of performance enhancement in independent double-gated poly-Si nanowire devices,&#x201D; IEEE Trans. Electron. Dev., vol.57, no.4, pp.905&#x2013;912, 2010.","DOI":"10.1109\/TED.2010.2041857"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] S.-I. Kuroki, X. Zhu, K. Kotani, and T. Ito, &#x201C;Enhancement of current drivability of nanograting polycrystalline silicon thin-film transistors,&#x201D; Jpn. J. Appl. Phys., vol.49, no.4S, pp.04DJ11-1&#x2013;04DJ11-5, 2010.","DOI":"10.1143\/JJAP.49.04DJ11"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] H. J. H. Chen, J.-R. Jhang, C.-J. Huang, S.-Z. Chen, and J.-C. Huang, &#x201C;Poly-Si TFTs with three-dimensional finlike channels fabricated using nanoimprint technology,&#x201D; IEEE Electron Device Lett., vol.32, no.2, pp.155&#x2013;157, 2011.","DOI":"10.1109\/LED.2010.2090333"},{"key":"25","unstructured":"[25] A. Hara, T. Sato, K. Kondo, K. Hirose, and K. Kitahara, &#x201C;Self-aligned metal double-gate low-temperature polycrystalline silicon thin-film transistors on glass substrate using back-surface exposure,&#x201D; Jpn. J. Appl. Phys., vol.50, no.2R, pp.021401-1&#x2013;021401-4, 2011."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] Y.-H. Lu, P.-Y. Kuo, Y.-H. Wu, Y.-H. Chen, and T.-S. Chao, &#x201C;Novel sub-10-nm gate-all-around Si nanowire channel poly-Si TFTs with raised source\/drain,&#x201D; IEEE Electron Device Lett., vol.32, no.2, pp.173&#x2013;175, 2011.","DOI":"10.1109\/LED.2010.2093557"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] T.-K. Kang, T.-C. Liao, C.-M. Lin, H.-W. Liu, and H.-C. Cheng, &#x201C;High-performance single-crystal-like nanowire poly-Si TFTs with spacer patterning technique,&#x201D; IEEE Electron Device Lett., vol.32, no.3, pp.330&#x2013;332, 2011.","DOI":"10.1109\/LED.2010.2099198"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] C.-J. Su, T.-I. Tsai, Y.-L. Liou, Z.-M. Lin, H.-C. Lin, and T.-S. Chao, &#x201C;Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,&#x201D; IEEE Electron Device Lett., vol.32, no.4, pp.521&#x2013;523, 2011.","DOI":"10.1109\/LED.2011.2107498"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H.-H. Hsu, H.-C. Lin, C.-W. Luo, C.-J. Su, and T.-Y. Huang, &#x201C;Impacts of multiple-gated configuration on the characteristics of poly-Si nanowire SONOS devices,&#x201D; IEEE Trans. Electron. Dev., vol.58, no.3, pp.641&#x2013;649, 2011.","DOI":"10.1109\/TED.2010.2098033"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] S. Fujii, S.-I. Kuroki, K. Kotani, and T. Ito, &#x201C;Strain-induced back channel electron mobility enhancement in polycrystalline silicon thin-film transistors fabricated by continuous-wave laser lateral crystallization,&#x201D; Jpn. J. Appl. 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