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ORCIDParallel Processing Letters, Volume 18, 2008
Volume 18, Number 1, March 2008
- Peter Krusche:
Experimental Evaluation of BSP Programming Libraries. 7-21 - Clemens Grelck, Steffen Kuthe, Sven-Bodo Scholz
:
A Hybrid Shared Memory Execution Model for a Data Parallel Language with I/O. 23-37 - Frédéric Gava:
A Modular Implementation of Data Structures in Bulk-Synchronous Parallel ML. 39-53 - Emmanuel Chailloux, Vivien Ravet, Julien Verlaguet:
Hirondml: Fair Threads Migrations for Objective Caml. 55-69 - Noemi de La Rocque Rodriguez, Silvana Rossetto:
Integrating Remote Invocations with Asynchronism and Cooperative Multitasking. 71-85 - Gagarine Yaikhom:
Message Passing without Memory Copy. 87-100 - Jost Berthold, Rita Loogen:
The Impact of Dynamic Channels on Functional Topology Skeletons. 101-115 - Michael Poldner, Herbert Kuchen:
On Implementing the Farm Skeleton. 117-131 - Ignacio Peláez, Francisco Almeida, Daniel González:
High Level Parallel Skeletons for Dynamic Programming. 133-147 - Roberto Di Cosmo, Zheng Li, Susanna Pelagatti, Pierre Weis:
Skeletal Parallel Programming with OCamlP3l 2.0. 149-164 - Sonia Campa:
Evaluating Computational Costs while Handling Data and Control Parallelism. 165-174 - Marco Aldinucci, Anne Benoit:
Automatic Mapping of Assist Applications Using Process Algebra. 175-188 - Wayne Goddard, Stephen T. Hedetniemi, David Pokrass Jacobs, Pradip K. Srimani, Zhenyu Xu:
Self-Stabilizing Graph Protocols. 189-199
Volume 18, Number 2, June 2008
- Jan Lemeire, Erik F. Dirkx, Walter Colitti:
Modeling the Performance of Communication Schemes on Network Topologies. 205-220 - Clemens Grelck, Sven-Bodo Scholz, Alexander V. Shafarenko:
A Gentle Introduction to S-Net: Typed Stream Processing and Declarative Coordination of Asynchronous Components. 221-237 - Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh:
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. 239-255 - Chris R. Jesshope:
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. 257-274 - Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle:
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips. 275-289 - Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong:
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs. 291-306 - F. Furman Haddix:
An Order Degree alternator for Arbitrary Topologies. 307-322
Volume 18, Number 3, September 2008
- Eugenio Zimeo, Alberto Troisi, Harris Papadakis, Paraskevi Fragopoulou, Agostino Forestiero, Carlo Mastroianni:
Cooperative Self-Composition and Discovery of Grid Services in P2P Networks. 329-346 - Serafeim Zanikolas, Rizos Sakellariou:
An Importance-Aware Architecture for Large-Scale Grid Information Services. 347-370 - Demetrios Zeinalipour-Yazti, Harris Papadakis, Chryssis Georgiou, Marios D. Dikaiakos:
Metadata Ranking and Pruning for Failure Detection in Grids. 371-390 - Fernando Costa, Luís Moura Silva, Gilles Fedak, Ian Kelley:
Optimizing Data Distribution in Desktop Grid Platforms. 391-410 - Boris Mejías, Peter Van Roy:
The Relaxed-Ring: a Fault-Tolerant Topology for Structured Overlay Networks. 411-432 - Zoltán Balaton, Zoltán Farkas, Gabor Gombás, Péter Kacsuk, Róbert Lovas, Csaba Attila Marosi, Ad Emmen, Gábor Terstyánszky, Tamás Kiss, Ian Kelley, Ian J. Taylor, Oleg Lodygensky, Miguel Cárdenas-Montes, Gilles Fedak, Filipe Araújo:
EdgES: the Common Boundary between Service and Desktop Grids. 433-445
Volume 18, Number 4, December 2008
- Alex K. Jones, Darren J. Kerbyson, Ramakrishnan Rajamony, Charles C. Weems:
Guest Editor's Note: Large-Scale Parallel Processing. 449-451 - Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren J. Kerbyson, Michael Lang, Scott Pakin, José Carlos Sancho:
A Performance Evaluation of the Nehalem Quad-Core Processor for Scientific Computing. 453-469 - Georg Hager, Thomas Zeiser, Gerhard Wellein:
Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems. 471-490 - Kevin Schaffer, Robert A. Walker:
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor. 491-509 - Noriyuki Fujimoto:
Dense Matrix-Vector Multiplication on the CUDA Architecture. 511-530 - John Michalakes, Manish Vachharajani:
Gpu Acceleration of Numerical Weather Prediction. 531-548 - Abhinav Bhatele, Laxmikant V. Kalé:
Benefits of Topology Aware Mapping for Mesh Interconnects. 549-566 - Alex K. Jones, Shuyi Shao, Yu Zhang, Rami G. Melhem:
Symbolic Expression Analysis for Compiled Communication. 567-587 - Darren J. Kerbyson, Michael Lang, Greg Johnson:
Infiniband Routing Table Optimizations for Scientific Applications. 589-608
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