default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID13th MTV 2012: Austin, TX, USA
- 13th International Workshop on Microprocessor Test and Verification, MTV 2012, Austin, TX, USA, December 10-13, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-4441-8
- Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco:
Architectural Trace-Based Functional Coverage for Multiprocessor Verification. 1-5 - Lukás Charvát, Ales Smrcka, Tomás Vojnar
:
Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description. 6-12 - Lyl M. Ciganda, Marco Gaudesi, Evelyne Lutton, Ernesto Sánchez, Giovanni Squillero, Alberto Paolo Tonda:
Automatic Generation of On-Line Test Programs through a Cooperation Scheme. 13-18 - Youngchul Cho, Seonghun Jeong, J. Jeong, Heejun Shim, Yenjo Han, Soojung Ryu, Jay Kim:
Case Study: Verification Framework of Samsung Reconfigurable Processor. 19-23 - Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng:
Deterministic ATPG for Low Capture Power Testing. 24-29 - Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang:
Dual-LFSR Reseeding for Low Power Testing. 30-34 - Georges Morbé, Christoph Scholl:
Guaranteeing Termination of Fully Symbolic Timed Forward Model Checking. 35-40 - Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Localization of Bugs in Processor Designs Using zamiaCAD Framework. 41-47 - Markus Mattwandel:
New Process to Simultaneously Measure, Quantify, and Model Energy Efficient Performance. 48-53 - Nicola Bombieri, Emad Samuel Malki Ebeid, Franco Fummi, Michele Lora:
On the Reuse of RTL IPs for SysML Model Generation. 54-59 - Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen:
Two-Way Multicasting for Test Data Compression. 60-64 - Heejun Shim, Minwook Ahn, JinSae Jung, Yenjo Han, Soojung Ryu:
Verification of CGRA Executable Code and Debugging of Memory Dependence Violation. 65-69 - Johnny J. W. Kuan, Tor M. Aamodt:
Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug. 70-75 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco:
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis. 76-81
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-04-17 23:10 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
