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ORCID1. PARLE 1987: Eindhoven, The Netherlands - Volume 1
- J. W. de Bakker, A. J. Nijman, Philip C. Treleaven:
PARLE, Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 15-19, 1987, Proceedings. Lecture Notes in Computer Science 258, Springer 1987, ISBN 3-540-17943-7 - Geoffrey E. Hinton:
Learning Translation Invariant Recognition in Massively Parallel Networks. 1-13 - Martin Rem:
Trace Theory and Systolic Computations. 14-33 - Emile H. L. Aarts, Jan H. M. Korst:
Boltzmann Machines and their Applications. 34-50 - Paul Anderson, Chris Hankin, Paul H. J. Kelly, Peter Osmon, Malcolm J. Shute:
COBWEB-2: Structured Specification of a Wafer-Scale Supercomputer. 51-67 - J. K. Annot, Rob A. H. van Twist:
A Novel Deadlock Free and Starvation Free Packet Switching Communication Processor. 68-85 - Pier Giorgio Bosco, Egidio P. Giachin, G. Giandonato, G. Martinengo, Claudio Rullent:
A Parallel Architecture for Signal Understanding through Inference on Uncertain Data. 86-102 - Werner Damm, Gert Döhmen:
An Axiomatic Approach to the Specification of Distributed Computer Architectures. 103-120 - Frank K. H. A. Dehne, Jörg-Rüdiger Sack, Nicola Santoro:
Computing on a Systolic Screen: Hulls, Contours and Applications. 121-133 - Jean-Luc Gaudiot, Liang-Teh Lee:
Multiprocessor Systems Programming in a High-Level Data-Flow Language. 134-151 - Peter A. J. Hilbers, Marion R. J. Koopman, Jan L. A. van de Snepscheut:
The Twisted Cube. 152-159 - Chua-Huang Huang, Christian Lengauer:
An Implemented Method for Incremmental Systolic Design. 160-177 - J. K. Iliffe:
The Use of Parallel Functions in System Design. 178-194 - Anne Kaldewaij:
The Translation of Processes into Circuits. 195-212 - Ottmar Krämer, Heinz Mühlenbein:
Mapping Strategies in Message Based Multiprocessor Systems. 213-225 - Simon H. Lavington, M. Standing, Y. J. Jiang, C. J. Wang, M. E. Waite:
Hardware Memory Management for Large Knowledge Bases. 226-241 - D. L. McBurney, M. Ronan Sleep:
Transputer-Based Experiments with the ZAPP Architecture. 242-259 - Catherine Mongenet, Guy-René Perrin:
Synthesis of Systolic arrays for Inductive Problems. 260-277 - David J. Pritchard, C. R. Askew, D. B. Carpenter, Ian Glendinning, Anthony J. G. Hey, Denis A. Nicole:
Practical Parallelism using Transputer Arrays. 278-294 - Sanjay V. Rajopadhye, Richard Fujimoto:
Systolic Array Synthesis by Static Analysis of Program Dependencies. 295-310 - Peter Schaefer, Philippe Schnoebelen:
Specification of a Pipelined Event Driven Simulator using FP2. 311-328 - Per Stenström, Lars H. Philipson:
A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory. 329-344 - Jack A. Test, Mat Myszewski, Richard C. Swift:
The Alliant FX/Series: A Language Driven Architecture for Parallel Processing of Dusty Deck Fortran. 345-356 - Peter H. Welch:
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance). 357-373 - Marco Bellia, Pier Giorgio Bosco, Elio Giovannetti, Giorgio Levi, Corrado Moiso, Catuscia Palamidessi
:
A Two-Level Approach to Logic plus Functional Programming Integration. 374-393 - David I. Bevan, Geoffrey Livingston Burn, R. J. Karia:
Overview of a Parallel Reduction Machine Project. 394-413 - Rubén González-Rubio, Jean Rohmer, A. Bradier:
An Overview of DDC: Delta Driven Computer. 414-433 - Philippe Jorrand:
Design and Implementaion of a Parallel Inference Machine for First Order Logic: An Overview. 434-445 - P. Mehring, E. Aposporidis:
Multi-Level Simulator for VLSI - An Overview. 446-460 - Eddy Odijk:
The DOOM System and its Applications: A Survey of Esprit 415 Subproject A, Philips Research Laboratries. 461-479
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