default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID22nd RSP 2011: Karlsruhe, Germany
- Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011. IEEE 2011, ISBN 978-1-4577-0658-5
Session 1: Automotive & FPGA
- Sazzadur Chowdhury, Roberto Muscedere, Sundeep Lal:
An FPGA-based signal processing system for a 77 GHz MEMS tri-mode automotive radar. 2-8 - Alexander Bochem, Kenneth B. Kent
, Rainer Herpers:
FPGA based real-time object detection approach with validation of precision and performance. 9-15 - Felix Mühlbauer, Michael Großhans, Christophe Bobda:
Rapid prototyping of OpenCV image processing applications using ASP. 16-22 - Ming Zhang, Zonghua Gu:
Optimization issues in mapping AUTOSAR components to distributed multithreaded implementations. 23-29 - Alexander Bochem, Kenneth B. Kent, Yves G. Losier, Jeremy Williams, Justin Deschenes:
FPGA design for monitoring CANbus traffic in a prosthetic limb sensor network. 30-36
Session 2: Prototyping Architectures
- Jakub Szefer, Wei Zhang, Yu-Yuan Chen, David Champagne, King Chan, Will X. Y. Li, Ray C. C. Cheung, Ruby B. Lee:
Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform. 38-44 - Owen Callanan, Antonio Castelfranco, Catherine H. Crawford, Eoin Creedon, Scott Lekuch, Kay Müller, Mark Nutter, Hartmut Penner, Brian Purcell, Mark Purcell, Jimi Xenidis:
A study in rapid prototyping: Leveraging software and hardware simulation tools in the bringup of system-on-a-chip based platforms. 45-52 - Matthias Heinz, Martin Hillenbrand, Kai Klindworth, Klaus D. Müller-Glaser:
Rapid automotive bus system synthesis based on communication requirements. 53-58 - Taha Beyrouthy, Laurent Fesquet:
An event-driven FIR filter: Design and implementation. 59-65
Session 3: Prototyping Radio Devices
- William Plishker, George F. Zaki, Shuvra S. Bhattacharyya, Charles Clancy, John Kuykendall:
Applying graphics processor acceleration in a software defined radio prototyping environment. 67-73 - Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz:
Validation of channel decoding ASIPs a case study. 74-78 - Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Area and throughput optimized ASIP for multi-standard turbo decoding. 79-84 - François Philipp, Faizal Arya Samman, Manfred Glesner:
Design of an autonomous platform for distributed sensing-actuating systems. 85-90
Session 4: Virtual Prototyping for MPSoC
- Tennessee Carmel-Veilleux, Jean-François Boland, Guy Bois:
A novel low-overhead flexible instrumentation framework for virtual platforms. 92-98 - João Moreira, Felipe Klein, Alexandro Baldassin, Paulo Centoducatte, Rodolfo Azevedo, Sandro Rigo:
Using multiple abstraction levels to speedup an MPSoC virtual platform simulator. 99-105 - Damien Hedde, Frédéric Pétrot:
A non intrusive simulation-based trace system to analyse Multiprocessor Systems-on-Chip software. 106-112 - Alexandra Aguiar, Felipe Gohring de Magalhaes, Fabiano Hessel:
Embedded virtualization for the next generation of cluster-based MPSoCs. 113-119
Session 5: Model Based System Design
- Daniel Balasubramanian, Gábor Pap, Harmon Nine, Gabor Karsai, Michael R. Lowry, Corina S. Pasareanu, Thomas Pressburger:
Rapid property specification and checking for model-based formalisms. 121-127 - Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich:
Automatic generation of system-level virtual prototypes from streaming application models. 128-134 - Francisco Mendoza, Christian Köllner, Jürgen Becker, Klaus D. Müller-Glaser:
An automated approach to SystemC/Simulink co-simulation. 135-141 - Tobias Schwalb, Klaus D. Müller-Glaser:
Extension of component-based models for control and monitoring of embedded systems at runtime. 142-148 - Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser:
A model-driven based framework for rapid parallel SoC FPGA prototyping. 149-155 - Sébastien Le Nours, Anthony Barreteau, Olivier Pasquier:
A state-based modeling approach for fast performance evaluation of embedded system architectures. 156-162
Session 6: Software for Embedded Devices
- Alexandre M. Amory, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski:
Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time. 164-170 - Hui Chen, Guillaume Godet-Bar, Frédéric Rousseau, Frédéric Pétrot:
Me3D: A model-driven methodology expediting embedded device driver development. 171-177
Session 7: Tools and Designs for Configurable Architectures
- Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Schedulers-Driven approach for dynamic placement/scheduling of multiple DAGs onto SoPCs. 179-185 - Junyan Tan, Virginie Fresse, Frédéric Rousseau:
Generation of emulation platforms for NoC exploration on FPGA. 186-192 - Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Arbitration and routing impact on NoC design. 193-198 - Surapong Pongyupinpanich, Manfred Glesner:
On-chip efficient Round-Robin scheduler for high-speed interconnection. 199-202
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-04-01 23:22 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
