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ORCIDShiyu Zhao 0004
Person information
- affiliation: Hefei Boya Semiconductor Technology Co., Ltd, Anhui , Hefei, China
Other persons with the same name
- Shiyu Zhao — disambiguation page
- Shiyu Zhao 0001
![[0000-0002-4978-725X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-4978-725X")
— Meta (and 1 more) - Shiyu Zhao 0002 — Westlake University, Hangzhou, China
- Shiyu Zhao 0003 — Shenyang Jianzhu University, China
- Shiyu Zhao 0005 — Beijing University of Technology, Beijing, China
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2020 – today
- 2025
[j4]Shiyu Zhao, Qiang Zhao, Licai Hao, Hao Wang, Lang Tian, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
A double-modules interlocking triple-node upset-tolerant latch design. Microelectron. J. 159: 106647 (2025)- [j3]Licai Hao, Lang Tian, Hao Wang, Shiyu Zhao, Qiang Zhao, Chunyu Peng, Chenghu Dai, Zhi-Ting Lin, Xiulong Wu:
A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate. IEEE Trans. Very Large Scale Integr. Syst. 33(4): 1108-1117 (2025) - 2024
- [j2]Shiyu Zhao, Qiang Zhao, Licai Hao, Chunyu Peng, Yaling Wang, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
Design of polarity hardening SRAM for mitigating single event multiple node upsets. Microelectron. J. 149: 106214 (2024) - [j1]Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024)
Coauthor Index
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