Bhupendra Singh Reniwal

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Vikas Vijayvargiya

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Publications

2019
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Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi:
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019)
2018
[j4]
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Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62: 1-13 (2018)
2017
[j3]
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Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13(1): 47-59 (2017)
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Bhupendra Singh Reniwal, Pooran Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID 2017: 335-340
2016
[j1]
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Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35(9): 3066-3085 (2016)
2015
[c4]
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Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I_cell SRAM Using FinFET. ACM Great Lakes Symposium on VLSI 2015: 95-98

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