Yusang Chun

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Mohamed Megahed

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Publications

2025
[c6]
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Ehung Chen, Henry Park, Mohammed Abdullatif, Miguel Gandara, Ahmed ElShater, Amr Khashaba, Shih-Hao Huang, Tsz-Bin Liu, Atharav Atharav, Joonyeong Lee, Qaiser Nehal, Mohamed Megahed, Yusang Chun, Cheng-En Shieh, Vidhan Jolly, SoonWon Kwon, Hsin-Ta Chien, Ke-Chung Wu, Cheng-En Liu, Peng Yan, Po-Jui Li, Chun-Han Chen, Tzu-Shun Lin, Pei-Chieh Liu, Tamer A. Ali:
7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. ISSCC 2025: 1-3
2024
[j4]
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Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand:
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. IEEE J. Solid State Circuits 59(8): 2492-2505 (2024)
2022
[j3]
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Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits 57(5): 1527-1541 (2022)
2021
[c4]
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Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand:
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. VLSI Circuits 2021: 1-2
[c3]
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Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand:
A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. VLSI Circuits 2021: 1-2
2020
[j1]
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Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand:
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1946-1959 (2020)

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