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ORCIDWeidong Cao 0001
Person information
- affiliation: George Washington University, Department of Electrical and Computer Engineering,
- affiliation (PhD 2021): Washington University in St. Louis, Department of Electrical and Systems Engineering, St. Louis, MO, USA
Other persons with the same name
- Weidong Cao (aka: Wei-Dong Cao) — disambiguation page
- Weidong Cao 0002
![[0000-0002-0394-9639]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-0394-9639")
— Hohai University, College of Artificial Intelligence and Automation, Nanjing, China (and 1 more)
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2020 – today
- 2026
[j8]Tianrui Ma, Zhe Gao, Zhe Chen, Ramakrishna Kakarala, Charles Shan, Weidong Cao, Xuan Zhang:
Systematic Methodology of Modeling and Design Space Exploration for CMOS Image Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 45(2): 1047-1060 (2026)- 2025
- [j7]Weidong Cao, Jian Gao, Tianrui Ma, Rui Ma, Mouhacine Benosman, Xuan Zhang:
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(2): 627-640 (2025) - [c20]Jian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao, Xuan Zhang:
EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits. DAC 2025: 1-7 - [c19]Shikai Wang, Yaolong Hu, Zhiqiang Yi, Taiyun Chi, Weidong Cao:
Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog Circuits. DAC 2025: 1-2 - [c18]Jian Gao, Weidong Cao, Junyi Yang, Xuan Zhang:
AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies. ICLR 2025 - [c17]Jian Gao, Weidong Cao, Xuan Zhang:
AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling. ICML 2025 - [c16]Yiwen Liang, Zhiqiang Yi, Tianrui Ma, Weidong Cao:
LoRASensE: Learnable Low-Rank Acquisition in Sensors for Efficient Edge Machine Vision. ISLPED 2025: 1-7 - [i10]Zhiqiang Yi, Yiwen Liang, Weidong Cao:
A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks. CoRR abs/2502.07212 (2025) - [i9]Jian Gao, Weidong Cao, Junyi Yang, Xuan Zhang:
AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies. CoRR abs/2503.00205 (2025) - 2024
- [j6]Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang:
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1191-1205 (2024) - [j5]Xiaoyu Sun, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong:
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. ACM Trans. Design Autom. Electr. Syst. 29(6): 1-27 (2024) - [c15]Weidong Cao, Jian Gao, Xin Xin, Xuan Zhang:
Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition. DAC 2024: 156:1-156:6 - [i8]Weidong Cao, Jian Gao, Tianrui Ma, Rui Ma, Mouhacine Benosman, Xuan Zhang:
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning. CoRR abs/2407.19150 (2024) - 2023
- [c14]Jian Gao, Weidong Cao, Xuan Zhang:
RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning. DAC 2023: 1-6 - [c13]Huifeng Zhu, Weidong Cao, Xuan Zhang:
PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures. ICCAD 2023: 1-8 - [c12]Zehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao, Yixin Chen, Xuan Zhang:
CktGNN: Circuit Graph Neural Network for Electronic Design Automation. ICLR 2023 - [c11]Tianrui Ma, Adith Jagadish Boloor, Xiangxing Yang, Weidong Cao, Patrick Williams, Nan Sun, Ayan Chakrabarti, Xuan Zhang:
LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge. ISCA 2023: 54:1-54:14 - [c10]Weidong Cao, Hua Wang, Xuan Zhang:
Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning. ISCAS 2023: 1-5 - [c9]Weidong Cao, Xuan Zhang:
A/D Alleviator: Reducing Analog-to-Digital Conversions in Compute-In-Memory with Augmented Analog Accumulation. ISCAS 2023: 1-5 - [i7]Weidong Cao, Hua Wang, Xuan Zhang:
Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning. CoRR abs/2301.12101 (2023) - [i6]Zehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao, Yixin Chen, Xuan Zhang:
CktGNN: Circuit Graph Neural Network for Electronic Design Automation. CoRR abs/2308.16406 (2023) - 2022
- [j4]Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang:
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. IEEE Trans. Computers 71(9): 2142-2155 (2022) - [c8]Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma:
Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization. DAC 2022: 1015-1020 - [c7]Huifeng Zhu, Zhiyuan Yu, Weidong Cao, Ning Zhang, Xuan Zhang:
PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on Touchscreens. ICCAD 2022: 67:1-67:9 - [c6]Tianrui Ma, Weidong Cao, Fei Qiao, Ayan Chakrabarti, Xuan Zhang:
HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors. ISLPED 2022: 10:1-10:6 - [i5]Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang:
Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals. CoRR abs/2201.12861 (2022) - [i4]Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma:
Domain Knowledge-Based Automated Analog Circuit Design with Deep Reinforcement Learning. CoRR abs/2202.13185 (2022) - [i3]Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma:
Domain Knowledge-Infused Deep Learning for Automated Analog/Radio-Frequency Circuit Parameter Optimization. CoRR abs/2204.12948 (2022) - [i2]Weidong Cao, Changqing Wang, Weijian Chen, Song Hu, Hua Wang, Lan Yang, Xuan Zhang:
Demonstration of fully integrated parity-time-symmetric electronics. CoRR abs/2205.09498 (2022) - 2021
- [j3]Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang:
Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 808-821 (2021) - 2020
- [j2]Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang:
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1841-1854 (2020)
2010 – 2019
- 2019
- [c5]Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang:
NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support. DATE 2019: 1477-1482 - [c4]Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang:
Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices. ICCAD 2019: 1-7 - [i1]Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang:
Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices. CoRR abs/1911.12815 (2019) - 2018
- [j1]Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang:
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. 82: 36-45 (2018) - 2016
- [c3]Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang:
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS 2016: 1-4 - 2015
- [c2]Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang:
A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS 2015: 1-4 - [c1]Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang:
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS 2015: 1-4
Coauthor Index
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