<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/irps/SungHLYLSGC25" mdate="2025-06-04">
<author>C. H. Sung</author>
<author>M. J. Huang</author>
<author>Y. J. Li</author>
<author>Y. T. Yang</author>
<author>Y. R. Liu</author>
<author>P. H. Shih</author>
<author>J. C. Guo</author>
<author>Steve S. Chung</author>
<title>Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation.</title>
<pages>1-6</pages>
<year>2025</year>
<booktitle>IRPS</booktitle>
<ee>https://doi.org/10.1109/IRPS48204.2025.10982918</ee>
<crossref>conf/irps/2025</crossref>
<url>db/conf/irps/irps2025.html#SungHLYLSGC25</url>
</inproceedings>
</dblp>
