Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.

Pierre-Emmanuel Gaillardon Hassan Ghasemzadeh 0002 Giovanni De Micheli Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. 1-6 2013 LATW https://doi.org/10.1109/LATW.2013.6562673 https://doi.ieeecomputersociety.org/10.1109/LATW.2013.6562673 conf/latw/2013 db/conf/latw/latw2013.html#GaillardonGM13