<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<article key="journals/jsa/ChatterjeePMC17" mdate="2020-02-24">
<author orcid="0000-0002-8402-8195">Navonil Chatterjee</author>
<author>Suraj Paul</author>
<author>Priyajit Mukherjee</author>
<author>Santanu Chattopadhyay</author>
<title>Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform.</title>
<pages>61-77</pages>
<year>2017</year>
<volume>74</volume>
<journal>J. Syst. Archit.</journal>
<ee>https://doi.org/10.1016/j.sysarc.2017.01.008</ee>
<url>db/journals/jsa/jsa74.html#ChatterjeePMC17</url>
</article></dblp>
