Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.

Tatsuhiko Ikeda

Toshiki Kanamoto Tatsuhiko Ikeda Akira Tsuchiya Hidetoshi Onodera Masanori Hashimoto Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. 3560-3568 2006 89-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e89-a.12.3560 db/journals/ieicet/ieicet89a.html#KanamotoITOH06

Tetsuro Kitazoe Sung-Ill Kim Yasunari Yoshitomi Tatsuhiko Ikeda Recognition of emotional states using voice, face image and thermal image of face. 653-656 2000 INTERSPEECH https://doi.org/10.21437/ICSLP.2000-162 conf/interspeech/2000 db/conf/interspeech/interspeech2000.html#KitazoeKYI00

Hisayasu Sato Kenichi Kashiwagi Kazuhito Niwano Tetsuya Iga Tatsuhiko Ikeda Koichiro Mashiko Tadashi Sumi Koji Tsuchihashi A 1.9-GHz single chip IF transceiver for digital cordless phones. 1974-1980 1996 31 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/4.545820 db/journals/jssc/jssc31.html#SatoKNIIMST96

Hisayasu Sato Kimio Ueda Nagisa Sasaki Tatsuhiko Ikeda Koichiro Mashiko A voltage compensated series-gate bipolar circuit operating at sub-2 V. 1200-1205 1994 October 29 IEEE J. Solid State Circuits 10 https://doi.org/10.1109/4.315203 db/journals/jssc/jssc29.html#SatoUSIM94

Yasunobu Nakase Kakutaro Suda Koichiro Mashiko Tatsuhiko Ikeda Shinpei Kayano A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. 518-524 1991 April 26 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.75049 db/journals/jssc/jssc26.html#NakaseSMIK91 streams/journals/jssc

Masanori Hashimoto Tetsuya Iga Toshiki Kanamoto Kenichi Kashiwagi Shinpei Kayano Sung-Ill Kim Tetsuro Kitazoe Koichiro Mashiko Yasunobu Nakase Kazuhito Niwano Hidetoshi Onodera Nagisa Sasaki Hisayasu Sato Kakutaro Suda Tadashi Sumi Koji Tsuchihashi Akira Tsuchiya Kimio Ueda Yasunari Yoshitomi