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Gayathri Chalivendra

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2010 – 2019

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2011
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Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula:
A new balanced 4-moduli set {2^k, 2ⁿ - 1, 2ⁿ + 1, 2ⁿ⁺¹-1} and its reverse converter design for efficient fir filter implementation. ACM Great Lakes Symposium on VLSI 2011: 139-144
2010
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Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula:
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI 2010: 210-215

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