"Fast estimation of area-delay trade-offs in circuit sizing."

Shrirang K. Karandikar, Sachin S. Sapatnekar (2005)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2005.1465402

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/KarandikarS05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/KarandikarS05
Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.