Dataset for article "New techniques to reduce cache interference in real-time mixed-criticality systems on multicore platforms"

This dataset correspond with the simulation results of a research work that addresses cache memory interference in mixed-criticality systems, especially in MpSoC architectures, by proposing new cache memory management techniques that outperform existing methods in mitigating the interference of non-critical tasks on real-time critical ones. Using the proposed techniques and a cache simulator, this work aims to improve the reliability of mixed-criticality systems in various industrial sectors.