adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Verilator open-source SystemVerilog simulator and lint system
RSD: RISC-V Out-of-Order Superscalar Processor
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
HW Design Collateral for Caliptra RoT IP