initial commit

Author: umarcor

control/run.sh

@@ -0,0 +1,13 @@
+#!/bin/sh
+
+cd $(dirname $0)
+
+mkdir -p wrk
+
+ghdl_args="--std=08 --workdir=wrk"
+
+ghdl -a $ghdl_args ./src/*
+ghdl -a $ghdl_args ./test/*
+
+ghdl --elab-run $ghdl_args tb --wave=wave.ghw
+

control/src/actuator.vhd

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+library ieee;
+context ieee.ieee_std_context;
+
+entity actuator is
+  port (
+    CLK: in  std_logic;
+    RST: in  std_logic;
+    EN:  in  std_logic;
+    I:   in  std_logic_vector(7 downto 0);
+    O:   out std_logic_vector(7 downto 0)
+  );
+end entity;
+
+architecture arch of actuator is
+
+begin
+
+O <= I;
+
+end arch;

control/src/hold.vhd

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+library ieee;
+context ieee.ieee_std_context;
+
+entity hold is
+  port (
+    CLK: in  std_logic;
+    RST: in  std_logic;
+    EN:  in  std_logic;
+    I:   in  std_logic_vector(7 downto 0);
+    O:   out std_logic_vector(7 downto 0)
+  );
+end entity;
+
+architecture arch of hold is
+
+begin
+
+O <= I;
+
+end arch;

control/src/pid.vhd

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+library ieee;
+context ieee.ieee_std_context;
+
+entity pid is
+  port ( CLK, RST, EN: in std_logic;
+         R,I: in std_logic_vector(7 downto 0);
+		 O: out std_logic_vector(7 downto 0)
+	   );
+end entity;
+
+architecture arch of pid is
+
+type t_q is array (natural range 2 downto 0) of signed(7 downto 0);
+type t_e is array (natural range 2 downto 0) of signed(7 downto 0);
+type t_eq is array (natural range 2 downto 0) of signed(15 downto 0);
+type t_u is array (natural range 1 downto 0) of signed(18 downto 0);
+
+constant q: t_q:=("00000100","00000010","00000010");
+signal e: t_e;
+signal eq: t_eq;
+signal u: t_u;
+
+signal s0: signed(16 downto 0);
+signal s1: signed(17 downto 0);
+signal uraw: signed(19 downto 0);
+
+begin
+
+e(0) <= signed(R)-signed(I);
+
+process(CLK) begin if rising_edge(CLK) then
+  if rst then
+    u(1) <= (others=>'0');
+    e(2) <= (others=>'0');
+    e(1) <= (others=>'0');
+  elsif EN then
+    u(1) <= u(0);
+    e(2 downto 1) <= e(1 downto 0);
+  end if;
+end if;	end process;
+
+ms: for i in 0 to 2 generate
+  eq(i) <= e(i) * q(i);
+end generate;
+
+s0 <= resize(eq(0),s0'length) + eq(1);
+s1 <= resize(s0,s1'length) + eq(2);
+
+uraw <= resize(s1,uraw'length) + u(1);
+
+u(0) <= uraw(18 downto 0) when (uraw(19) xnor uraw(18)) else
+     (18 => '0', others=>'1') when (not uraw(19)) else
+   (18 => '1', 0 => '1', others=>'0');
+
+O <= std_logic_vector(u(0)(18 downto 11));
+
+end arch;

control/src/plant.vhd

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+library ieee;
+context ieee.ieee_std_context;
+
+entity plant is
+  port ( CLK, RST, EN: in std_logic;
+         I: in std_logic_vector(7 downto 0);
+		 O: out std_logic_vector(7 downto 0)
+	   );
+end entity;
+
+architecture arch of plant is
+  signal s: std_logic_vector(7 downto 0);
+begin
+
+process(CLK) begin if rising_edge(CLK) then
+  if RST then
+    s <= (others=>'0');
+  elsif EN then
+    s <= std_logic_vector(signed(s)+1) when signed(I)>0 else std_logic_vector(signed(s)-1) when signed(I)<0 else s;
+  end if;
+end if; end process;
+
+O <= s;
+
+end arch;

control/src/sys.vhd

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+library ieee;
+context ieee.ieee_std_context;
+
+entity sys is
+  port ( CLK, RST: in std_logic;
+         R: in std_logic_vector(7 downto 0)
+	   );
+end entity;
+
+---
+
+library ieee;
+context ieee.ieee_std_context;
+
+architecture arch of sys is
+  signal i, u, o, p: std_logic_vector(7 downto 0);
+  signal cnt_c, cnt_p: unsigned(7 downto 0);
+  signal en_c, en_o, en_p, en_i: std_logic;
+begin
+
+m_c: entity work.pid
+  port map ( CLK, RST, en_c, R, i, u );
+
+m_o: entity work.actuator
+  port map ( CLK, RST, en_o, u, o );
+
+m_p: entity work.plant
+  port map ( CLK, RST, en_p, o, p );
+
+m_i: entity work.hold
+  port map ( CLK, RST, en_i, p, i );
+
+p_clks: process(CLK) begin if rising_edge(CLK) then
+  if RST then
+    cnt_c <= (others=>'0');
+    cnt_p <= (others=>'0');
+  else
+    cnt_c <= (others=>'0') when cnt_c?=9 else cnt_c+1;
+    cnt_p <= (others=>'0') when cnt_c?=90 else cnt_p+1;
+  end if;
+end if; end process;
+
+en_c <= cnt_c?=1;
+en_o <= '1';
+en_p <= cnt_p?=1;
+en_i <= '1';
+
+end arch;

control/test/tb.vhd

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+--http://ctms.engin.umich.edu/CTMS/index.php?example=MotorSpeed&section=ControlDigital
+--https://dsp.stackexchange.com/questions/14965/how-to-implement-a-filter-in-matlab
+--http://stackoverflow.com/questions/22236977/latex-math-in-github-wikis
+--
+
+entity tb is
+end entity;
+
+---
+
+library ieee;
+context ieee.ieee_std_context;
+
+architecture arch of tb is
+ constant t: time:= 10 ns;
+ signal clk, rst, done: std_logic:='0';
+ signal r: std_logic_vector(7 downto 0):=(others=>'1');
+begin
+
+p_clk: process begin
+  clk <= '1'; wait for t/2;
+  clk <= '0'; wait for t/2;
+  if done then wait; end if;
+end process;
+
+p_rst: process begin
+  rst <= '1'; wait for 10*t;
+  rst <= '0'; wait for 5 ms;
+  if done then wait; end if;
+end process;
+
+p_main: process begin
+  r <= std_logic_vector(to_signed(0,8)); wait for 1 us;
+  r <= std_logic_vector(to_signed(63,8)); wait for 1 ms;
+  r <= std_logic_vector(to_signed(127,8)); wait for 1 ms;
+
+  assert false report "end of test" severity note;
+  done <= '1';
+  --  Wait forever; this will finish the simulation.
+  wait;
+end process;
+
+uut: entity work.sys port map ( clk, rst, r );
+
+end arch;