Bridging HW and SW verification with VUnit co-simulation.pdf
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Modelling closed-loop control systems with VHDL Sharing data between VHDL and a foreign engine
TEXT/CSV.
Ad-hoc read/write procedures.
Might need to convert integer to/from fixed-point.
BIN.
Waveform.
Post-morten (or streaming).
Limited type representations.
JSON-for-VHDL.
Cosimulation.
In subdir control, execute python run.py -v.
tb_soft_singleproctb_soft_singleproc_bintb_soft_singleproc_binvec (does not work)tb_soft_twoproc
In Matlab, go to subdir control/m.
Execute plant.m.
Execute step_p.m.
fsys_p: proportional, continuous plant.fsys_d: proportional, discrete plant.man_ss: hardcoded controller, discrete plant.man_diffe: hardcoded controller, hardcoded plant.hdl: generated by tb_soft_singleproc_bin.
In subdir control, execute python3 run.py -v -g lib.tb_soft_twoproc_bin.all.
AXI-Lite
Structural
Fixed-point
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