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Melkie WalelignAn Introduction to Computer Systems
David Vernon
Copyright 2007 David Vernon (www.vernon.eu)
A Computer ....
takes input processes it according to stored instructions produces results as output
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Input: Data Instructions: Software, Programs Output: Information (numbers, words, sounds, images)
Copyright 2007 David Vernon (www.vernon.eu)
Types of Computer
Computer
Special Purpose (embedded systems) Pre-programmed
General Purpose (user-programmable) Can be adapted to many situations
Watches
Traffic Signals
Personal Computers
Workstations
Engine Management
Televisions
Mainframes
Supercomputers
Telephones
Navigation Devices
Copyright 2007 David Vernon (www.vernon.eu)
Data vs Information
A
2, 4, 23, 30, 31, 36
A
your grade in the exam
2, 4, 23, 30, 31, 36
Next weeks Lotto numbers
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Codes
Data and information can be represented as electrical signals (e.g. Morse code) A code is a set of symbols (such as dots and dashes in Morse code) that represents another set of symbols,
such as the letters of the alphabet, or integers or real numbers, or light in an image, for the tone of a violin
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
A circuit is an inter-connected set of electronic components that perform a function Integrated Circuits (ICs)
Combinations of thousands of circuits built on tiny pieces of silicon called chips
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Binary signal (two state signal)
Data with two states off & on low voltage & high voltage 0v & 5v
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Bit
Single Binary Digit Can have value 0 or 1, and nothing else A bit is the smallest possible unit of information in a computer
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Groups of bits can represent data or information
1 bit - 2 alternatives 2 bits - 4 alternatives 3 bits - 8 alternatives 4 bits - 16 alternatives n n bits - 2 alternativies 8 8bits - 2 = 256 alternatives a group of 8 bits is called a byte
Copyright 2007 David Vernon (www.vernon.eu)
4 Bits
0000 0001 0010 0011 0100 0101 0110 0111
1000 1001 1010 1011 1100 1101 1110 1111
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Information System
A system that takes data, stores and processes it, and provides information as an output An IS is a computer in use The amount of data can be vast
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Communication System
Communication: the transfer of meaningful information Comprises
a sender (transmitter) a channel over which to send the data a receiver
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Network
Two and usually more communication devices connected together Many connection topologies
Copyright 2007 David Vernon (www.vernon.eu)
Key Concepts
Hardware
The physical (electronic and mechanical) parts of a computer or information system
Software
The programs that control the operation of the computer system
Copyright 2007 David Vernon (www.vernon.eu)
Components of Computer Systems
Copyright 2007 David Vernon (www.vernon.eu)
Components of Computer Systems
Keyboard Display System Unit Storage Printer
Copyright 2007 David Vernon (www.vernon.eu)
Key Components
More Formally:
Input Output Storage Processor
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Keyboard
Keyboard
Most common input device QWERTY
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INPUT
Input Systems
Keyboard
Mouse
Mouse
Cursor manipulation device Trackball
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INPUT
Input Systems
Keyboard Touch Screen
Mouse
Touch Screens
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INPUT
Input Systems
Keyboard Touch Screen
Mouse Pen/Stylus
Pens Stylus
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INPUT
Input Systems
Keyboard Touch Screen Magnetic Ink
Mouse Pen/Stylus
Magnetic Ink Character Recognition (MICR)
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Keyboard Touch Screen Magnetic Ink
Mouse Pen/Stylus Bar Code
Bar Code Readers
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Optical Character Recognition systems Book readers for the blind Automated input of text Can do typewritten text and handwritten block capital Problems with cursive handwriting recognition
Keyboard
Mouse
Touch Screen
Pen/Stylus
Magnetic Ink
Bar Code
Optical Character Recognition
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Sensors
Digital thermometers Accelerometers Strain gauges (weighing scales) ....
Keyboard
Mouse
Touch Screen
Pen/Stylus
Magnetic Ink
Bar Code
Optical Character Recognition
Sensors
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Camera Systems
Surveillance and monitoring Visual inspection Robot guidance Video conferencing
Keyboard
Mouse
Touch Screen
Pen/Stylus
Magnetic Ink
Bar Code
Optical Character Recognition Cameras
Sensors
Copyright 2007 David Vernon (www.vernon.eu)
INPUT
Input Systems
Voice
Voice recognition Hands-free car-phones Assistance for the disabled
Keyboard
Mouse
Touch Screen
Pen/Stylus
Magnetic Ink
Bar Code
Optical Character Recognition Cameras
Sensors
Voice
Copyright 2007 David Vernon (www.vernon.eu)
Key Components
Input Output Storage Processor
Copyright 2007 David Vernon (www.vernon.eu)
Output Systems
OUTPUT
Soft Copy
Modem
Disk or Tape
Hard Copy
Copyright 2007 David Vernon (www.vernon.eu)
OUTPUT
Output Systems
Voice
Soft Copy
Modem
Disk or Tape
Hard Copy
CRT
Flat Panel
Soft Copy
Voice synthesis Music CRT (Cathode Ray Tube) LCD (Liquid Crystal Display)
Copyright 2007 David Vernon (www.vernon.eu)
OUTPUT
Output Systems
Voice
Soft Copy
Modem
Disk or Tape
Hard Copy
CRT
Flat Panel
Modems
Modulator-Demodulator Allows computers to communicate over telephone lines
Copyright 2007 David Vernon (www.vernon.eu)
OUTPUT
Output Systems
Voice
Soft Copy
Modem
Disk or Tape
Hard Copy
CRT
Flat Panel
Disks
Magnetic
Floppy Hard disk
Optical
Storage Devices
Copyright 2007 David Vernon (www.vernon.eu)
Output Systems
OUTPUT
Soft Copy
Modem
Disk or Tape
Hard Copy
Voice
CRT
Flat Panel
Plotters
Microfilm
Non-impact Printers
Impact Printers
Copyright 2007 David Vernon (www.vernon.eu)
Output Systems
OUTPUT
Soft Copy
Modem
Disk or Tape
Hard Copy
Voice
CRT
Flat Panel
Plotters
Microfilm
Non-impact Printers
Impact Printers
Copyright 2007 David Vernon (www.vernon.eu)
Output Systems
OUTPUT
Soft Copy
Modem
Disk or Tape
Hard Copy
Voice
CRT
Flat Panel
Plotters
Microfilm
Non-impact Printers
Impact Printers
Laser Thermal Transfer
Magnetic Thermal and Electrostatic
Copyright 2007 David Vernon (www.vernon.eu)
Output Systems
Soft Copy Modem
OUTPUT
Disk or Tape
Hard Copy
Voice
CRT
Flat Panel
Plotters
Microfilm
Non-impact Printers
Impact Printers
Dot matrix
Line Printer
Copyright 2007 David Vernon (www.vernon.eu)
Key Components
Input Output Storage Processor
Copyright 2007 David Vernon (www.vernon.eu)
Storage Systems
STORAGE
Units of Storage
1 bit 8 bits = 1 byte 10 1kbyte = 2 = 1024 bytes 20 1Mbyte = 2 = 1048576 bytes
Temporary MEMORY
Permanent MASS STORAGE
Copyright 2007 David Vernon (www.vernon.eu)
Storage Systems
STORAGE
Memory
Temporary MEMORY
Permanent MASS STORAGE
Stores the bits and bytes (instructions and data) ROM ROM - Read Only Memory
Non-volatile Wont disappear when power is off
RAM
RAM - Random Access Memory
Read/Write Memory Volatile SIMMs (Single Inline Memory Modules): 4 Mbytes in a stick of chewing gum
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
Temporary MEMORY
Permanent MASS STORAGE
Optical Disks
ROM
RAM
Optical
Magnetic
15,000 tracks per inch Digital code read by laser 650 Mbytes in a 4.75 plastic platter CD ROM; WORM; Erasable Disks
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
Temporary MEMORY
Permanent MASS STORAGE
CD ROM
ROM
RAM
Optical
Magnetic
CD Read Only Memory 12cm optical disk Capable of storing 72 minutes of VHS quality video using MPEG compression
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
Temporary MEMORY
Permanent MASS STORAGE
Write-One Read_Mostly CDs (WORMS)
ROM
RAM
Optical
Magnetic
Powerful laser burns in the digital code Not erasable Lowe power laser reads the digital pattern
Eraseable CD
Lasers read and write inofrmation Also use a magnetic material To write: a laser beam heats a tiny spot and a magnetic field is applied to reverse the magnetic polarity
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
ROM
Temporary MEMORY
Permanent MASS STORAGE
RAM
Optical
Magnetic
Disk
Memory Card
Magnetic Disk
A circular platter coated with magnetic material
Tape
Floppy Disk
3.5; 360kbyte to 2.88Mbytes (1.44 is common)
Hard Disk
1.3, 1.8, 2.5, 3.5, 5.25; 120Mbytes to over 6 Gigabyte (6 Gbyte)
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
ROM
Temporary MEMORY
Permanent MASS STORAGE
RAM
Optical
Magnetic
Disk
Memory Card
40 Gbyte hard disk
20,000,000 pages of text
Tape
650 Mbyte CD
325,000 pages of text
17 Gbyte DVD
8,500,000 pages of text
Copyright 2007 David Vernon (www.vernon.eu)
STORAGE
Storage Systems
ROM
Temporary MEMORY
Permanent MASS STORAGE
RAM
Optical
Magnetic
Height of Read Head above magnetic surface
2 millionths of an inch
Disk Tape
Memory Card
Smoke Particle
250 millionths of an inch
Fingerprint
620 millionths of an inch
Dust particle
1500 millionths of an inch
Human hair
3000 millionths of an inch
Copyright 2007 David Vernon (www.vernon.eu)
The Processor: Hardware & Software
Copyright 2007 David Vernon (www.vernon.eu)
Components of Computer Systems
Keyboard Display System Unit Storage Printer
Copyright 2007 David Vernon (www.vernon.eu)
Key Components
Input Output Storage Processor
Copyright 2007 David Vernon (www.vernon.eu)
Processing Unit
Hardware
Hardware
Software
Microprocessor
Effects computation Intel 80486, 80586 Motorola 68040 PowerPC, MIPS, Alpha, Sparc Clock speeds 50-600MHz (+)
Microprocessor Memory Interface ICs
Memory
Storage
Interface ICs
communication with other devices
Copyright 2007 David Vernon (www.vernon.eu)
Processing Unit
Hardware
Hardware Software
Much more to come on the topic of hardware shortly
Microprocessor Memory Interface ICs
Copyright 2007 David Vernon (www.vernon.eu)
Software
Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Copyright 2007 David Vernon (www.vernon.eu)
Software
Operating Systems
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
User interfaces
Software which is responsible for passing information to and from the person using the program (the user) Communicates with and controls the computer Three types of user interface:
Graphic user interfaces Menu driven interfaces Command driven interfaces
Copyright 2007 David Vernon (www.vernon.eu)
Software
Operating Systems
Graphic User Interfaces (GUIs)
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Pictures, graphic symbols (icons), to represent commands Windows: a way of looking in on several applications at once
Copyright 2007 David Vernon (www.vernon.eu)
Software
Operating Systems
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Menu-driven interfaces
Menu bar Pull-down menu for choices
Copyright 2007 David Vernon (www.vernon.eu)
Software
Operating Systems
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Command-driven interfaces
A (system) prompt User types in single letter, word, line which is translated into an instruction for the computer For example: cp source destination Need to be very familiar with the syntax (grammar) of the command language
Copyright 2007 David Vernon (www.vernon.eu)
Software
Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
Operating System is the software that manages the overall operation of the computer system Main purpose is to support application programs Hide details of devices from application programs
Copyright 2007 David Vernon (www.vernon.eu)
Software
Operating Systems
Shell Network I/F
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Task Scheduler
Kernel
Shell (or user interface) Network interface: coordinate multiple tasks in a single computer Task scheduler coordination of multiple tasks in a single computer Kernel
Software which ties the hardware to the software, and manages the flow of information to and from disks, printers, keyboards, ... all I/O devices
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
File Handling
Collection of information (stored on disk) Disks need to be formatted to allow them to store information OS manages location of files on disk OS performs I/O to disk OS checks and corrects errors on disk I/O
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
Device Drivers
Programs which handle the various hardware devices, e.g., mouse, keyboard, CD, video, etc. For example, an application wants to print a document
It call the operating system which sends the information to the device driver together with instructions and the printer driver handles all the control of the printer
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
Single tasking OS
Runs only one application at a time
Multi-Tasking OS
More than one application can be active at any one time
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
DOS (Disk Operating System)
Single-tasking Command-driven Huge number of applications written for DOS Does not require powerful computer No network services No multimedia extensions Designed for the Intel 80x86 processor
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
Windows
GUI Can run DOS programs Has network services Has multimedia extensions Requires large amounts of memory, disk space, powerful processor Designed for the Intel 80X86 processors
Copyright 2007 David Vernon (www.vernon.eu)
Operating Systems
Macintosh OS
Multi-tasking GUI called finder Very easy to use Very graphically oriented Has network services Has multimedia extensions Designed for the Motorola and PowerPC processors
Copyright 2007 David Vernon (www.vernon.eu)
Software
Application Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Special Purpose
Payroll Accounting Book-Keeping Entertainment Statistical Analysis
Copyright 2007 David Vernon (www.vernon.eu)
Software
Application Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
General Purpose
Word Processing (e.g. MS Word) Desktop Publishing (e.g. Quark Xpress) Spreadsheets (e.g. MS Excel) Databases (e.g. MS Access) Graphics (e.g. MS Powerpoint) E-mail (e.g. MS Mail) Internet Browsers (e.g. Firefox, Explorer)
Copyright 2007 David Vernon (www.vernon.eu)
Software
Application Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Integrated Software
Goal: effective sharing of information between all applications For example: MS Office: Excel, Word, Powerpoint, Access can all use each others data directly
Copyright 2007 David Vernon (www.vernon.eu)
Software
Application Software
System Software
Application Software
Operating Systems
Programming Languages
General Purpose
Special Purpose
Integrated Software
Object Linking & Embedding (OLE) Information is stored in one location only Reference is made to it from another application This reference is known as a link Dont actually make a copy (cf. hypertext, multimedia, WWW)
Copyright 2007 David Vernon (www.vernon.eu)
Application Software
Object Linking & Embedding (OLE)
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Operation of Processor and Memory
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
The processor is a functional unit that interprets and carries out instructions Also called a Central Processing Unit (CPU) Every processor has a unique set of operations LOAD ADD STORE
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
This set of operation is called the instruction set Also referred to as machine instructions The binary language in which they are written is called machine language
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
An instruction comprises
operator (specifies function) operands - (data to be operated on)
For example, the ADD operator requires two operands
Must know WHAT the two numbers are Must know WHERE the two numbers are
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
If the data (e.g. the number to be added) is in memory, then the operand is called an address ADD num1 num2 num1 could be a number or it could be the address of a number in memory (i.e. where the number is stored)
Copyright 2007 David Vernon (www.vernon.eu)
Machine Language Instruction Set
Category Arithmetic Logic Program Control Data Movement Input/Output Example Add, subtract, multiply, divide And, or, not, exclusive or branching, subroutines Move, load, store Read, Write
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
The processors job is to
retrieve instructions from memory retrieve data (operands) from memory perform the operation (maybe store the result in memory) retrieve the next instruction ....
Copyright 2007 David Vernon (www.vernon.eu)
The Processor
This step-by-step operation is repeated over and over at speeds measured in millionths of a second The CLOCK governs the speed: each step must wait until the clock ticks to begin a 300 MHz processor will use a clock which ticks 300 000 000 times a second
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input MEMORY Output
CPU Control Unit Arithmetic & Logic Unit ALU Registers
Copyright 2007 David Vernon (www.vernon.eu)
The Control Unit
Supervises the operation of the processor Makes connections between the various components Invokes the operation of each component Can be interrupted!
Copyright 2007 David Vernon (www.vernon.eu)
The Control Unit
An interrupt
is a signal which tells the control unit to suspend execution of its present sequence of instructions (A) and to transfer to another sequence (B) resuming the original sequence (A) when finished with (B)
Copyright 2007 David Vernon (www.vernon.eu)
An Interrupt
Instruction A1 Instruction A2 Instruction A3 Instruction A4 Instruction A5 : : Instruction B1 Instruction B2 : : Instruction Bn
EXECUTE instructions BRANCH to new set of instructions
Copyright 2007 David Vernon (www.vernon.eu)
The Control Unit
Receives instructions from memory Decodes them (determines their type) Breaks each instruction into a sequence of individual actions (more on this later) And, in so doing, controls the operation of the computer.
Copyright 2007 David Vernon (www.vernon.eu)
The Arithmetic & Logic Unit
ALU Provided the computer with its computational capabilities Data are brought to the ALU by the control unit ALU performs the required operation
Copyright 2007 David Vernon (www.vernon.eu)
The Arithmetic & Logic Unit
Arithmetic operations
addition, subtraction, multiplication, division
Logic operations
make a comparison (CMP a, b) and take action as a result (BEQ same)
Copyright 2007 David Vernon (www.vernon.eu)
Registers
Register: a storage location inside the processor Control unit registers:
current instruction location of next instruction to be executed operands of the instruction
ALU registers:
store data items store results
Copyright 2007 David Vernon (www.vernon.eu)
Registers
Word size (or word length)
Size of the operand register Also used to describe the size of the pathways to and from the processor and between the components of the processor
16 to 64 bits word lengths are common 32 bit processor ... the operand registers of a processor are 32 bits wide (long!)
Copyright 2007 David Vernon (www.vernon.eu)
Specialized Processors
DSP - Digital Signal Processors
Image processing; sound, speech
Math co-processors
Real number arithmetic
ASICs - Application-Specific Integrated Circuits
Microwave contoller Engine management controller
Copyright 2007 David Vernon (www.vernon.eu)
The Operation of the Processor
A Simple Accumulator-Based CPU (Von Neumann Computer)
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input MEMORY Output
CPU Control Unit Arithmetic & Logic Unit ALU Registers
Copyright 2007 David Vernon (www.vernon.eu)
Main Components
(Program) Control Unit - PCU
Coordinates all other units in the computer Organizes movement of data from/to I/O, memory, registers. Directs ALU, specifically to indicate the operations to be performed The control unit operates according to the stored program, receiving and executing its instructions one at a time
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input MEMORY Output
CPU Control Unit Arithmetic & Logic Unit ALU Registers
Copyright 2007 David Vernon (www.vernon.eu)
Main Components
Arithmetic & Logic Unit - ALU
All computations are performed in this unit ALU comprises adders, counters, and registers Numerical operations (+ - / x) Logical operations (AND, OR, program branching)
Copyright 2007 David Vernon (www.vernon.eu)
Main Components
Register
Capable of receiving data, holding it, and transferring it as directed by the control unit
Adder
Receives data from two or more sources, performs the arithmetic, and sends the results to a register
Counter
Counts the number of times an operation is performed
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input MEMORY Output
INSTRUCTIONS Control Unit
DATA Arithmetic & Logic Unit ALU
Registers
CPU
Copyright 2007 David Vernon (www.vernon.eu)
Some Key Points
Instructions are coded as a sequence of binary digits Data are coded as a sequence of binary digits Registers are simply physical devices which allows these codes to be stored Memory is just the same
Copyright 2007 David Vernon (www.vernon.eu)
The Operation of a Processor
How does a computer evaluate a simple assignment statement? For example: A := B + C
Copyright 2007 David Vernon (www.vernon.eu)
The Operation of a Processor
A := B + C A computer cant evaluate this directly (because its not written in a way which matches the structure of the computers physical architecture) First, this must be translated into a sequence of instructions which the does match the computer architecture
Copyright 2007 David Vernon (www.vernon.eu)
The Operation of a Processor
A := B + C So ... we need a detailed processor architecture (i.e. a machine) and a matching language (machine language or assembly language)
machine language when its written as a binary code assembly language when its written symbolically.
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input MEMORY Output
INSTRUCTIONS Control Unit
DATA Arithmetic & Logic Unit ALU
Registers
CPU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
DR - Data Register AR - Address Register AC - Accumulator PC - Progam Counter IR - Instruction Register ALU - Arithmetic Logic Unit PCU - Program Control Unit
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
The Components of a Processor
Input CPU MEMORY Output
AR
DR
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
ALU
Copyright 2007 David Vernon (www.vernon.eu)
Instruction Format
An instruction is typically divided into 2 fields
address This is a opcode very simplified situation and, in general, one would expect opcode/operand opcode/address (which may vary in size)
Copyright 2007 David Vernon (www.vernon.eu)
Instruction Format
Load X
puts contents of memory location X into the accumulator
Add T
Add contents of memory at location T to the contents of the accumulator
Store Y
Put contents of accumulator into memory at location Y
Copyright 2007 David Vernon (www.vernon.eu)
Evaluate an Assignment
A := B + C Load B Add C Store A
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Input CPU
A 11111111
B 01001100
C 00000001 Output
AR
DR ALU
PCU Control Circuits
PC IR
AC
01001100
Arithmetic Logic Circuits
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Add C
Input CPU
A 11111111
B 01001100
C 00000001 Output
AR
DR ALU
PCU Control Circuits
PC IR
AC
01001101
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Store A
Input CPU
A 01001101
B 01001100
C 00000001 Output
AR
DR ALU
PCU Control Circuits
PC IR
AC
01001101
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
But .....
The instructions are stored in memory also!
Copyright 2007 David Vernon (www.vernon.eu)
Load B A Input CPU 11111111 B 01001100 C 00000001 Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
So .....
It works more like this ...
Copyright 2007 David Vernon (www.vernon.eu)
Evaluate an Assignment
A := B + C Load B Add C Store A
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Load B
Input CPU
A 11111111
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Load B
AC Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Load B
Input CPU
A 11111111
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Load B
AC
01001100
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Add C
Input CPU
A 11111111
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Add C
AC
01001100
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Add C
Input CPU
A 11111111
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Add C
AC
01001101
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Store A
Input CPU
A 11111111
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Store A
AC
01001101
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B
Store A
Input CPU
A 01001101
B 01001100
C 00000001
Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR Store A
AC
01001101
Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Load B A Input CPU 11111111 B 01001100 C 00000001 Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
Copyright 2007 David Vernon (www.vernon.eu)
Operation of the Processor
The primary function of a processor is to execute sequences of instructions stored in main memory Instruction Cycle
Fetch Cycle Execute Cycle
Copyright 2007 David Vernon (www.vernon.eu)
Instruction Cycle
Fetch Cycle
Fetch instruction from memory
Execute Cycle
Decode instruction Fetch required operands Perform operation
Copyright 2007 David Vernon (www.vernon.eu)
Instruction Cycle
Instruction cycle comprises a sequence of micro-operations each of which involves a transfer of data to/from registers
Copyright 2007 David Vernon (www.vernon.eu)
Instruction Cycle
In addition to executing instructions the CPU supervises other system component usually via special control lines It controls I/O operations (either directly or indirectly) Since I/O is a relatively infrequent event, I/O devices are usually ignored until they actively request service from the CPU via an interrupt
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An Interrupt
Instruction A1 Instruction A2 Instruction A3 Instruction A4 Instruction A5 : : Instruction B1 Instruction B2 : : Instruction Bn Interrupt is activated by an electronic signal EXECUTE instructions BRANCH to new set of instructions
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START Instruction Awaiting Execution? NO YES Fetch next instruction Execute next instruction Interrupts requiring servicing? NO YES Transfer control to interrupt handling program
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Instruction Cycle
FETCH CYCLE EXECUTE CYCLE
PROGRAM TRANSFER
Main Program
Subroutine A
Interrupt Handler
Load B Add C Store A Output CPU
OP1 OP1 OP1 Output AR
OP1 OP1 OP1 Output DR
A 11111111 B 01001100 C 00000001
ALU PCU Control Circuits PC IR AC Arithmetic Logic Circuits
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Register Transfer Language
Storage locations, in CPU and memory, are referred to by an acronym AC
Accumulator; main operand register of ALU
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Register Transfer Language
DR
Data Register; acts as a buffer between CPU and main memory. It is used as an input operand register with accumulator to facilitate operations of the form AC f(AC, DR)
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Register Transfer Language
PC
Program Counter Stores address of the next instruction to be executed
IR
Instruction Register Holds the opcode of the current instruction
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Register Transfer Language
AR
Address Register Holds the memory address of an operand
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Register Transfer Language
AB
transfer contents of storage location B to A (copy operation)
AM(ADR)
transfer contents of memory at location ADR to location A
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START CPU Activated? YES AR PC DR M(AR) IR DR(opcode) increment PC decode instruction ADD instruction? NO STORE instruction? NO
FETCH CYCLE
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START
EXECUTE CYCLE
ADD instruction? YES AR DR(Address) DR M(AR) AC AC + DR
NO
STORE instruction? YES YES PC DR(Address)
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Evaluate an Assignment
A := B + C
Load B Add C Store A
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A := B + C
Load B
AR PC DR M(AR) IR DR(opcode) Increment PC Decode instruction in IR AR DR(address) DR M(AR) AC DR
FETCH
EXECUTE
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A := B + C
Add C
AR PC DR M(AR) IR DR(opcode) Increment PC Decode instruction in IR AR DR(address) DR M(AR) AC AC + DR
FETCH
EXECUTE
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A := B + C
Store A
AR PC DR M(AR) IR DR(opcode) Increment PC Decode instruction in IR AR DR(address) DR AC M(AR) DR
FETCH
EXECUTE
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Load B
Input CPU
AR PC
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR ALU
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
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Load B
Input CPU
DR M(AR)
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
Load B ALU
PCU Control Circuits
PC IR
AC Arithmetic Logic Circuits
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Load B
Input CPU
IR DR(opcode)
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
Load B ALU
PCU Control Circuits
PC IR Load
AC Arithmetic Logic Circuits
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Load B
Input CPU
Increment PC
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
Load B ALU
PCU Control Circuits
PC IR Load
AC Arithmetic Logic Circuits
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Load B
Input CPU
Decode Instruction
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
Load B ALU
PCU Control Circuits
PC IR Load
AC Arithmetic Logic Circuits
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Load B
Input CPU
AR DR(address)
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
Load B ALU
PCU Control Circuits
PC IR Load
AC Arithmetic Logic Circuits
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Load B
Input CPU
DR M(AR)
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
01001100 ALU
PCU Control Circuits
PC IR Load
AC Arithmetic Logic Circuits
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Load B
Input CPU
AC DR
A 11111111 B 01001100 C 00000001
Load B Add C Store A Output
AR
DR
01001100 ALU
PCU Control Circuits
PC IR Load
AC
01001100
Arithmetic Logic Circuits
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Extensions to the Basic Organization and Binary Number Representations
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Extensions
Additional addressable registers for storing operands and addresses If these are multipurpose, we have what is called a General Register Organization Sometimes special additional registers are provided for the purpose of memory address construction (e.g. index register)
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Extensions
The capabilities of the ALU circuits can be extended to include multiplication and division The ALU can process floating point (real) numbers as well as integers Additional registers can be provided for storing instructions (instruction buffer)
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Extensions
Special circuitry to facilitate temporary transfer to subroutines or interrupt handling programs and recovery of original status of interrupted program on returning from interrup handler e.g. the use of a push-down stack implies that we need only a special-purpose stack pointer register
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Extensions
Parallel processing Simultaneous processing of two or more distinct instructions or data streams
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Information Representation
Types of data
Text Numbers
Integers Reals (floating point numbers)
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Text
ASCII code (American Standard Committee on Information Interchange) A unique 8-bit binary code for each character:
A-Z, a-z, 1-9, .,!$$%^&*()_+ Special unprintable characters such as the ENTER key (CR for carriage return)
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Numbers
Binary number representation of integers If we save one bit to signify positive (+) or negative (-), then an n-bit binary word can represent integers in the range -2n-1 -1 .. +2n-1
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Numbers
For example, a 16-bit binary number can represent integers in the range -216-1 -1 .. +216-1 = -215 -1 .. +215 -32,767 .. +32,768
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Numbers
A 16-bit binary number
0000 0001 1001 1111
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Numbers
A 16-bit binary number
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000 0001 1001 1111
= 1 x 2 8+ 1 x 2 7+ 1 x 2 4+ 1 x 2 3+ 1 x 2 2 + 1 x 2 1+ 1 x 2 0 = 256 + 128 + 16 + 8 + 4 + 2 + 1 = 415
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Numbers
If we let the most significant bit (MSB) signify positive or negative numbers (1 for negative; 0 for positive) Then +9 = 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 -9 = 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 +9 + (-9) = 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Which is NOT zero .... a problem!
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Numbers
So we need a different representation for negative numbers Called 2s-complement Take the 1s-complement of the positive number: 0000 0000 0000 1001 becomes 1111 1111 1111 0110
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Numbers
Note that the addition of the 1s-complement and the original number is not zero 0000 0000 0000 1001 + 1111 1111 1111 0110 __________________________ 1111 1111 1111 1111
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Numbers
To get the 2s-complement, add 1 1111 1111 1111 0110 + 1 __________________________ 1111 1111 1111 0111
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Numbers
Now do the addition: 0000 0000 0000 1001 + 1111 1111 1111 0111 __________________________ 0000 0000 0000 0000
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Numbers
Another example: +1 + (-1) 0000 0000 0000 0001 + 1111 1111 1111 1111 __________________________ 0000 0000 0000 0000
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Numbers
Short-hand for all these 1s and 0s HEX notation Each group of 4 bits represents a number in the range 0 - 15
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Numbers
0000= 0001= 0010= 0011= 0100= 0101= 0110= 0111= 0 1 2 3 4 5 6 7 1000= 1001= 1010= 1011= 1100= 1001= 1110= 1111= 8 9 A B C D E F
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Numbers
Thus: 0000 0000 0000 1001 1111 1111 1111 0111 __________________________ 0000 0000 0000 0000 0009 FFF7 ____ 0000
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Numbers
And: 0000 0000 0000 0001 1111 1111 1111 1111 __________________________ 0000 0000 0000 0000 0001 FFFF ____ 0000
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Numbers
Hex is used as a notation for any sequence of bits (e.g. ASCII characters require just two hex digits)
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Digital Design
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Design Hierarchy
Many digital systems can be divided into three design levels that form a well-defined hierarchy
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Design Hierarchy
The Architecture Level High-level concerned with overall system management The Logic Level Intermediate level concerned with the technical details of the system The Physical Level Low level concerned with the details needed to manufacture or assemble the system
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Design Hierarchy
We have already studied the architecture level Now we will address the logic level At the logic level, there are two classes of digital system
Combinational - digital systems without memory Sequential - digital systems with memory
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Analogue and Digital Signals
An analogue signal can have any value within certain operating limits For example, in a (common emitter) amplifier, the output (O/P) can have any value between 0v and 10v. A digital signal can only have a fixed number of values within certain tolerances
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Analogue and Digital Signals
Amplitude
An analogue signal The amplitude is defined at all moments in time
Time
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Analogue and Digital Signals
Amplitude
A digital signal It is a sampled version of the analogue signal Only defined at certain discrete times DISCRETE TIME SIGNAL
Time
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Analogue and Digital Signals
A digital signal is a sampled version of the analogue signal
Amplitude
Time
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Analogue and Digital Signals
Amplitude
The amplitude may also be restricted to take on discrete values only In which case it is said to be quantized
Time
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Analogue and Digital Signals
Quantization introduces errors which depend on the step size or the resolution
Amplitude
Time
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Analogue and Digital Signals
Amplitude
Signals (voltages or currents) which are samples and quantized are said to be DIGITAL They can be represented by a sequence of numbers
Time
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Analogue and Digital Signals
Calculation with numbers is usually done in base 10 arithmetic Easier to effect machine computation in base 2 or binary notation We can also use base 2 or binary notation to represent logic values: TRUE and FALSE Manipulation of these (digital) logic values is subject to the laws of logic as set out in the formal rules of Boolean algebra
Copyright 2007 David Vernon (www.vernon.eu)
Boolean Algebra
Definition: a logic variable x can have only one of two possible values or states
x = TRUE x = FALSE
In binary notation, we can say
x = TRUE = 1 x = FALSE = 0
This is called positive logic or high-true logic
Copyright 2007 David Vernon (www.vernon.eu)
Boolean Algebra
We could also say
x = TRUE = 0 x = FALSE = 1
This is called negative logic or low-true logic Usually we use the positive logic convention
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Boolean Algebra
Electrically,
1 is represented by a more positive voltage than zero and 0 is represented by zero volts
x = TRUE = 1 = 5 volts x = FALSE = 0 = 0 volts
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Logic Gates
Logic gates are switching circuits that perform certain simple operations on binary signals These operations are chosen to facilitate the implementation of useful functions
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Logic Gates
The AND logic operation Consider the following circuit
A + _ B Bulb
The bulb = ON = TRUE when A AND B are TRUE (i.e. closed)
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Logic Gates
The AND Truth Table
A 0 0 1 1
B 0 1 0 1
f = A AND B 0 0 0 1
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Logic Gates
The AND Gate
A B
f= A.B
A and B are variables and note the use of the . to denote AND
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Logic Gates
The AND Gate - An example Determine the output waveform when the input waveforms A and B are applied to the two inputs of an AND gate
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Logic Gates
The AND Gate - An example Determine the output waveform when the input waveforms A and B are applied to the two inputs of an AND gate
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Logic Gates
The OR logic operation
A + _
B Bulb
The bulb = ON = TRUE if either A OR B are TRUE (i.e. closed)
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Logic Gates
The OR Truth Table
A B f = A OR B 0 0 1 1 0 1 0 1 0 1 1 1
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Logic Gates
The OR Gate
A B
f= A+B
A and B are variables and note the use of the + to denote OR
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Logic Gates
The NOT Truth Table
A 0 1
f = NOT A 1 0
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Logic Gates
The NOT Gate
f= A
Note the use of the bar over the A to denote NOT
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Logic Gates
Sometimes a bubble is used to indicate inversion
AA B
f= A
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Logic Gates
In fact it is simpler to manufacture the combination NOT AND and NOT OR than it is to deal with AND and OR NOT AND becomes NAND NOT OR becomes NOR
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Logic Gates
The NAND Truth Table
A 0 0 1 1
B 0 1 0 1
f = A NAND B 1 1 1 0
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Logic Gates
The NAND Gate
A B
f= A.B
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Logic Gates
The NOR Truth Table
A B f = A NOR B 0 0 1 1 0 1 0 1 1 0 0 0
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Logic Gates
The NOR Gate
A B
f= A+B
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Logic Gates
The EXCLUSIVE OR Truth Table f = A XOR B =A = +
A B f = A XOR B 0 0 1 1 0 1 0 1 0 1 1 0
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Logic Gates
The XOR Gate
A B
f= AB
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Logic Gates
The EXCLUSIVE NOR Truth Table f = NOT (A XOR B) =A = +
A B f = A XOR B 0 0 1 1 0 1 0 1 1 0 0 1
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Logic Gates
The EXCLUSIVE NOR Gate
A B
f= AB
This is called the equivalence gate
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Rules and Laws of Boolean Algebra
Operations on Boolean variables are defined by rules and laws, the most important of which are presented here Commutative Law
A.B=B.A A+B=B+A
This states that the order of the variables is unimportant
Copyright 2007 David Vernon (www.vernon.eu)
Rules and Laws of Boolean Algebra
Associative Law
A . (B . C) = A . (B . C) A + (B + C) = A + (B + C)
This states that the grouping of the variables is unimportant
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Rules and Laws of Boolean Algebra
Distributive Law
A . (B + C) = A . B + A . C
This states that we can remove the parenthesis by multiplying through The above laws are the same as in ordinary algebra, where + and . are interpreted as addition and multiplication
Copyright 2007 David Vernon (www.vernon.eu)
Rules and Laws of Boolean Algebra
Basic rules involving one variable: A+0=AA.0=0 A+1=1 A.1=A A+A=A A.A=A A+A=1A+A=0
It should be noted that A = A
Copyright 2007 David Vernon (www.vernon.eu)
Rules and Laws of Boolean Algebra
An informal proof of each of these rules is easily accomplished by taking advantage of the fact that the variable can have only two possible values For example, rule 2: A+1=1 If A = 0 then 0 + 1 = 1 If A = 1 then 1 + 1 = 1
Copyright 2007 David Vernon (www.vernon.eu)
Rules and Laws of Boolean Algebra
Some useful theorems A + A.B = A A + A.B = A + B A.B + A.B = A A(A + B) = A A(A + B) = A.B (A+B)(A+B) = A These may be proved in a similar manner
Copyright 2007 David Vernon (www.vernon.eu)
Rules and Laws of Boolean Algebra
For example: A + A.B = A+B
A 0 0 1 1
B 0 1 0 1
A 1 1 0 0
A.B A+A.B A+B 0 1 0 0 0 1 1 1 0 1 1 1
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Rules and Laws of Boolean Algebra
Finally, we come to DeMorgans Laws which are particularly useful when dealing with NAND and NOR logic They are stated as follows
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DeMorgans Laws (1)
A+B=A.B Read as:
NOT (A OR B) = NOT A AND NOT B A NOR B = NOT A AND NOT B
Relates NOT, OR, and AND Can be extended to any number of variables A + B + C ... = A . B . C . ....
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DeMorgans Laws (1)
u
A+B=A.B
A 0 0 1 1 B 0 1 0 1 A+B A+B A 0 1 1 1 B A.B
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DeMorgans Laws (1)
u
A+B=A.B
A 0 0 1 1 B 0 1 0 1 A+B A+B A 0 1 1 1 1 0 0 0 B A.B
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DeMorgans Laws (1)
u
A+B=A.B
A 0 0 1 1 B 0 1 0 1 A+B A+B A 0 1 1 1 1 0 0 0 1 1 0 0 B A.B
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DeMorgans Laws (1)
u
A+B=A.B
A 0 0 1 1 B 0 1 0 1 A+B A+B A 0 1 1 1 1 0 0 0 1 1 0 0 B 1 0 1 0 A.B
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DeMorgans Laws (1)
u
A+B=A.B
A 0 0 1 1 B 0 1 0 1 A+B A+B A 0 1 1 1 1 0 0 0 1 1 0 0 B 1 0 1 0 A.B 1 0 0 0
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DeMorgans Laws (2)
A.B=A+B Read as:
NOT (A AND B) = NOT A OR NOT B A NAND B = NOT A OR NOT B
Relates NOT, OR, and AND Can be extended to any number of variables A . B . C ... = A + B + C . ....
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DeMorgans Laws (2)
u
A.B=A+B
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A.B A B A+B
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DeMorgans Laws (2)
u
A.B=A+B
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A.B 1 1 1 0 A B A+B
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DeMorgans Laws (2)
u
A.B=A+B
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A.B 1 1 1 0 A 1 1 0 0 B A+B
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DeMorgans Laws (2)
u
A.B=A+B
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A.B 1 1 1 0 A 1 1 0 0 B 1 0 1 0 A+B
Copyright 2007 David Vernon (www.vernon.eu)
DeMorgans Laws (2)
u
A.B=A+B
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A.B 1 1 1 0 A 1 1 0 0 B 1 0 1 0 A+B 1 1 1 0
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DeMorgans Laws
A+B=A.B Let A be I won the Lotto Let B be Im happy The the first DeMorgan Law tell us that: NOT (I won the Lotto OR Im happy) is the same as NOT(I won the lotto) AND NOT(Im happy) [or: I didnt win the lotto and Im not happy]
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DeMorgans Laws
A . B = A+ B Let A be I won the Lotto Let B be Im happy The the second DeMorgan Law tell us that: NOT (I won the Lotto AND Im happy) is the same as NOT(I won the lotto) OR NOT(Im happy) [or: I didnt win the lotto OR Im not happy]
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DeMorgans Laws
A B
A+B
A B
A.B
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DeMorgans Laws
A B
A+B
A B
A.B
A B
A.B
A B
A+B
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DeMorgans Laws
Taking the NAND gate as an example, we can derive effective AND-OR gating although physically we are using only one type of gate For example f = A.B + C.D
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DeMorgans Laws
A B
A.B (A.B) . (C.D) = (A.B) + (C.D) =
C D
C.D
A.B
+ C.D
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DeMorgans Laws
A B
A.B (A.B) . (C.D) = (A.B) + (C.D) =
C D
C.D
A.B
+ C.D
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DeMorgans Laws
This is referred to as NAND/NAND gating Any logic equation may be implemented using NAND gates only Thus NAND gates may be regarded as univeral gates The same is true for NOR gates
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DeMorgans Laws
Other advantages of using NAND or NOR gating are: Simplest and cheapest to fabricate Fastest operating speed Lowest power dissipation
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Simplification of Expressions using Boolean Algebra
It is important to minimise Boolean functions as this often brings about a reduction in the number of gates or inputs that are needed For example: consider AB + A(B+C) + B(B+C)
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Simplification of Expressions using Boolean Algebra
AB + A(B+C) + B(B+C) AB + AB + AC + BB + BC {distribution} AB + AC + BB + BC {X + X = X } AB + AC + B + BC {X . X = X } AB + B.1 + BC + AC {X . 1 = X } B(A+1+C) + AC {distribution} B.1 + AC {1 + X = 1 } B + AC {X . 1 = X }
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Simplification of Expressions using Boolean Algebra
Consider: (AB(C + BD) + AB)C (ABC + ABBD + AB)C {distribution} ABCC + ABBCD + ABC {distribution} ABC + ABBCD + ABC {X.X = X } ABC + A0CD + ABC {X.X = 0 } ABC + ABC {0.X = 0 } BC(A + A) {distribution} BC {X+X = 1 }
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Simplification of Expressions using Boolean Algebra
In general: Multiply out and collect common terms Exactly as you would do when simplifying ordinary algebraic expressions
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Expression of Problems using Boolean Algebra
Most real problems are defined using a sentential structure. It is therefore necessary to translate such sentences into Boolean equations if we are to derive a digital circuit to give a Boolean result.
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Expression of Problems using Boolean Algebra
For example It will snow IF it is cloudy AND it is cold. The IF and the AND divide the sentence into different phrases Let: f = it will snow = 1, if true; 0 if false A = it is cloudy = 1, if true; 0 if false B = it is cold = 1, if true 0 if false So f = A.B
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Corresponding Digital Circuit
A (cloud detector) B (cold detector)
f (activate snow warning)
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Expression of Problems using Boolean Algebra
A slightly more complicated example: An alarm circuit is to be designed which will operate as follows The alarm will ring IF the alarm switch is on AND the door is open, or IF it is after 6pm AND the window is open
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
Lets give the clauses some labels, just as before The alarm will ring (f)
IF the alarm switch is on (A) AND the door is open (B), or IF it is after 6pm (C) AND the window is open (D)
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
f = the alarm will ring = 1, if true; 0 if false A = the alarm switch is on = 1, if true; 0 if false B = the door switch is open = 1, if true; 0 if false C = it is after 6 pm = 1, if true; 0 if false D = the window switch is open = 1, if true; 0 if false So f = A.B + C.D If f = 1, then the alarm will ring!
Copyright 2007 David Vernon (www.vernon.eu)
Corresponding Digital Circuit
A (alarm switch) B (door open detector) f (activate alarm) C (after 6 detector!) D (window open detector)
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Expression of Problems using Boolean Algebra
For more complicated problems, we define the problem coherently by constructing a truth table Well introduce the idea for this simple example and then go on to use it in a more complicated example
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Expression of Problems using Boolean Algebra
If we have a problem (or a Boolean expression) with four variables, then our truth table will look like this:
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Expression of Problems using Boolean Algebra
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Expression of Problems using Boolean Algebra
Each combination of the logical variables A, B, C, and D make a 4-bit binary number in the range 0-15 lets number each row with the equivalent decimal number
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Expression of Problems using Boolean Algebra
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Expression of Problems using Boolean Algebra
We could also add the equivalent Boolean expression For example: 0010 is equivalent to A.B.C.D
(in the following we will leave out the . for AND and just write ABCD)
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 _ _ __ AB C D _ _ _ AB C D _ _ _ AB C D _ _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D __ AB C D _ AB C D _ AB C D AB C D
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
We call each of these product terms a MINTERM Note that each minterm contains each input variable in turn We can express any Boolean expression in minterm form If f is expressed this way, we say it is in
sum of products form 1st Canonical Form
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 _ _ __ AB C D _ _ _ AB C D _ _ _ AB C D _ _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D __ AB C D _ AB C D _ AB C D AB C D Minterm m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
For example, in the case of the alarm circuit, we have: A = the alarm switch is on B = the door switch is open C = it is after 6 pm D = the window switch is open f = 1 = if A(=1) . B(=1) + C(=1) . D(=1) If f = 1, then the alarm will ring!
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
Then f = m3 + m7 + m11 + m12 + m13 + m14 + m15 Why? Because m3, m7, m11, and m15 are the minterm expressions when both C and D are 1 And m12, m13, and m14 are the minterm expressions when both A and B are 1 And the alarm should ring if any of these expressions occur, i.e., if f = AB + CD
Copyright 2007 David Vernon (www.vernon.eu)
Expression of Problems using Boolean Algebra
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 _ _ __ AB C D _ _ _ AB C D _ _ _ AB C D _ _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D _ __ AB C D _ _ AB C D _ _ AB C D _ AB C D __ AB C D _ AB C D _ AB C D AB C D Minterm m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Example courtesy of Dr. D. J. Furlong Department of Electronic and Electrical Engineering Trinity College, Dublin Ireland
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
The Cast:
Director of Public Health Systems Dr. Logik
The Scenario:
Overcrowded Public Health Clinic with many obviously ailing clients looking for a diagnosis ... Is it the dreaded Boolean virus? Or just Digital Flu? Or maybe just epidemic paranoia ....
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Director: Well, were going to have to do something ... I mean theres thousands of them out there either sick or just plain worried that they might be going to come down with some of the symptoms ... Youre the expert ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Ja, Ja, Ja, ... I know, but Im needed at all the other clinics too, you know. Look, why dont you get those clever engineering or computer science types of yours to build you an automated diagnostic system
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: so that all these good people can just enter their particular symptoms, if they have any, and be told electronically which medication, if any, to take ... Ja? Very simple, really.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Director: Well, I suppose it would be something .. but what if this computer scientist gets it wrong? I mean, if these people actually have this Boolean Virus then, - OK, we just prescribe Neominterm and theyll get over it. But if we give them Neominterm and they just have Digital Flu, or nothing at all, then theyll die. Its lethal stuff, you know
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Director: And if they have in fact got the Boolean Virus and we dont give them Neominterm then theyll croak it too ... And the symptoms are very similar ... I mean the chances of getting it wrong are so great and the consequences so drastic I really feel we have to have an expert like yourself here on site to check ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Look, its quite impossible that I should stay here and examine all these people. Calm down ... the problem is not that difficult to deal with. Youre just panicking. Relax ... Ill start things off for your computer scientist, but then I really must dash ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: You see, its like this. There are four symptoms: chills, rash, bloodshot eyes, and a fever. Now, anybody who hasnt got any of these symptoms doesnt have either Boolean Virus or Digital Flu. OK? Ja.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Anybody who has NO chill but HAS some of the other symptoms is just suffering from Digital Flu, so give them some DeMorgan salts and send them home. Ja? Good.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Now, if they DO have a chill, then youve got to look at the combination of symptoms ... Ja? OK! If there is a chill and a rash only, then its Digital Flu again.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: However, if its a chill by itself or a chill any any other combination of rash, bloodshot eyes, and fever, then theyve got the Boolean Virus for sure. Only Neominterm can save them then ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Director: That may be all very straightforward to you but how is my computer scientist going to design a foolproof system to distinguish Digital Flu from Boolean Virus?
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Look ... Im late as it is, but all that is required is a truth table with inputs and outputs like this
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Chills Rash Bloodshot Eyes Fever Boolean Virus Digital Flu
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: The outputs will be the Boolean Virus and Digital Flu indicators ... say a few little LEDs, Ja? Just hook them up to the system, along with the input symptom switches - one each for Chills, Rash, Bloodshot Eyes, and Fever, Ja? Then all the patients have to do is move the switch to True if they have a particular symptom, for False if not ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: Then the system will do the rest and either the Boolean Virus LED or the Digital Flu LED will go on unless of course they dont have any of these symptoms in which case theyre just scared and dont have either the Boolean Virus or the Digital Flu
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: So, If Boolean Virus THEN please take some Neominterm, ELSE IF Digital Flu THEN please take some DeMorgan Salts, ElSE just go home. Ja? Thats the way you computer people like to put things, isnt it? Ja? Simple!
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Director: Ja ... I mean Yes ... Dr. Logik: Right then. Im off. Good luck ... Oh ja, you might need this ... Director: A mirror? I dont follow you, Doctor.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Dr. Logik: The bloodshot eyes ... Theyll have to be able to examine their eyes, now wont they? Adieu ... Exeunt Dr. Logik ... Director rings Department of Computer Science Director: Can you send over a Computer Scientist right away, please?
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Enter Computer Scientist with puzzled look. Director: Ah, yes ... now look ... we need a system and its got to work as follows ... Director explains problem and gives Computer Scientist Dr. Logiks truth table sketch and mirror ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Computer Scientist: Yes, but as far as I remember the only logic gates we have in stock are NAND gates ... Director: Well, if I remember my college course in digital logic, that shouldnt necessarily be a problem, now should it?
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Computer Scientist: No? I mean No! er ... Yes, right ... Well, it depends ... Lets see whats in stores. I dont think theres very many of them at that ... Computer Scientist checks his laptop database ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Computer Scientist: 6 two-input, 2 three-input, and 1 four-input NAND gates .. Thats all! Power supply ... yep, Switches .. yep. LEDs ... yep. Box ... yep. Well, Ill just have to see if I can make it work with that lot. Director: Please do! Were depending on you ...
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Will the Computer Scientist be successful? Will the Director have to send for the National Guard to control the by now tense and growing crowd looking for diagnosis? Stay tuned!
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
There are four symptoms:
chills rash bloodshot eyes fever
There are two ailments:
Boolean Virus Digital Flu
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
Anybody who hasnt got any of these symptoms doesnt have either Boolean Virus or Digital Flu. Anybody who has NO chill but HAS some of the other symptoms is just suffering from Digital Flu, If there is a chill and a rash only, then its Digital Flu again. its a chill by itself or a chill any any other combination of rash, bloodshot eyes, and fever, then theyve got the Boolean Virus
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
Available Equipment
6 two-input NAND gates 2 three-input NAND gates 1 four-input NAND gate
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma and the Digital Doctor
We will address the problem in three way, just to compare efficiency and effectiveness: Straightforward (naive) implementation of the condition in gates Efficient implementation of the conditions in gates by simplifying the expressions Function minimization procedure using minterms and Karnaugh maps
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
There are four symptoms:
(A) chills (B) rash (C) bloodshot eyes (D) fever
There are two ailments:
(f1) Boolean Virus (f2) Digital Flu
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
Anybody who hasnt got any of these symptoms doesnt have either Boolean Virus or Digital Flu. NOT (A OR B OR C OR D) A+B+C+D Anybody who has NO chill but HAS some of the other symptoms is just suffering from Digital Flu f2 = A . (B + C + D)
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
If there is a chill and a rash only, then its Digital Flu again. f2 = A . B . C . D its a chill by itself or a chill and any other combination of rash, bloodshot eyes, and fever, (But not the Digital Flu combination of chill and rash only - NB) then theyve got the Boolean Virus f1 = A . B . C . D +A. ( B + C + D) . (B . C . D)
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
f1 = f1 = A . B . C . D +A. ( B + C + D) . (B . C . D) f2 = A . (B + C + D) f2 = A . B . C . D f1 = A . B . C . D +A. ( B + C + D) . (B . C . D) f2 = A . (B + C + D) + A . B . C . D
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
Our first implementation of this will be a direct gatingof these two Boolean expressions Note that in all of the following implementations, we will assume that both the value of an input variable (e.g. A or chill) and its logical inverse (e.g. A or NOT chill) are available
Copyright 2007 David Vernon (www.vernon.eu)
f1 = A . B . C . D +A. ( B + C + D) . (B . C . D)
Corresponding Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
f2 = A . (B + C + D) + A . B . C . D
Corresponding
Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f2
The Directors Dilemma Simplified Implementation
These two logic circuits are complicated! Can we do any better? Lets try to simplify the expressions.
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Simplified Implementation
f1 = A . B . C . D +A. ( B + C + D) . (B . C . D) f1 = A . B . C . D + (A.B + A.C + A.D).(B + C + D) f1 = A . B . C . D + A.B.B + A.C.B + A.D.B + A.B.C + A.C.C + A.D.C + A.B.D + A.C.D + A.D.D f1 = A . B . C . D + A.0 + A.C.B + A.D.B + A.B.C + A.C + A.D.C + A.B.D + A.C.D + A.D
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Simplified Implementation
f1 = A . B . C . D + 0 + A.(C.B + D.B + B.C + C + D.C + B.D + C.D + D ) f1 = A . B . C . D + A.(C.B + D.B + B.C + C + D.C + B.D + D ) f1 = A . B . C . D + A.(C.(B + B) + C + D.(B + C + B + 1 )) f1 = A . B . C . D + A.(C.1 + C + D.1 ) f1 = A . B . C . D + A.(C + D) f1 = A . B . C . D + A.C + A.D
Copyright 2007 David Vernon (www.vernon.eu)
f1 = A . B . C . D +A. ( B + C + D) . (B . C . D)
Corresponding Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
f1 = A . B . C . D + A.C + A.D Corresponding
Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
The Directors Dilemma Simplified Implementation
That simplification was hard work! Is there an easier way? Yes! We use truth-tables, minterms, and a simplification method known as Karnaugh maps
Copyright 2007 David Vernon (www.vernon.eu)
Anybody who hasnt got any of these symptoms doesnt have either Boolean Virus or Digital Flu Chills Rash Bloodshot Eyes Fever Boolean Virus Digital Flu
0 0 0 0 0 0
Copyright 2007 David Vernon (www.vernon.eu)
Anybody who has NO chill but HAS some of the other symptoms is just suffering from Digital Flu Chills Rash Bloodshot Eyes Fever Boolean Virus Digital Flu
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Copyright 2007 David Vernon (www.vernon.eu)
The Directors Dilemma Key Facts
If there is a chill and a rash only, then its Digital Flu again. Its a chill by itself or a chill and any other combination of rash, bloodshot eyes, and fever, (But not the Digital Flu combination of chill and rash only - NB) then theyve got the Boolean Virus
Copyright 2007 David Vernon (www.vernon.eu)
If there is a chill and a rash only, then its Digital Flu again ..... chill and other combinations - BV Chills Rash Bloodshot Eyes Fever Boolean Virus Digital Flu
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 f2 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 Minterm m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
A Karnaugh Map is simply another form of truth table Entry of each minterm Arranged in a 2-D array Each variable blocks in half of the array Different half for each variable With a 4-variable expression, we know there are 16 possible combinations or minterms
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
A= 0 A=1
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
B= 0
B=1
B= 0
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
C=0
C=1
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
D=0
D=1
D=0
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
01
D=1
11
C=1
10
B=1
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
m0 m1 m3 m2
m4 m5 m7 m6
m12 m8 m13 m9 D=1 m15 m11 m14 m10
01
11
C=1
10
B=1
Copyright 2007 David Vernon (www.vernon.eu)
Aside: 3-Variable Karnaugh Map
AB 00 01
A=1
11 10
m0 C=1 m1
m2 m3
m6 m7
m4 m5
B=1
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
To simplify a Boolean expression Express it as a (conventional) truth table Identify the minterms that are TRUE Identify the minterms that are FALSE Mark them as such in the Karnaugh Map And then ..........
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
Identify groups of adjacent 1s in the Karnaugh Map
Note that two squares are adjacent if they share a boundary (this includes the top and bottom edges and the left and right edges: top IS adjacent to bottom and left IS adjecent to right). For example, minterm 11 is adjacent to minterm 3
Try to get groups that are as large as possible(in blocks of 1, 2, 4, 8, ...)
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
Identify the least number of variables that are required to unambiguously label that group The simplified expression is then the logical OR of all the terms that are needed to identify each (largest as possible) group of 1s Note: groups may overlap and this sometimes helps when identifying large groups
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 f2 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 Minterm m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Copyright 2007 David Vernon (www.vernon.eu)
Simplification using Minterms and Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
m0 m1 m3 m2
m4 m5 m7 m6
m12 m8 m13 m9 D=1 m15 m11 m14 m10
01
11
C=1
10
B=1
Copyright 2007 David Vernon (www.vernon.eu)
f1 = A . B . C . D +A. ( B + C + D) . (B . C . D)
Karnaugh
Maps
AB 00 CD 00 01
A=1
11 10
0 0 0 0
0 0 0 0
0 1 1 1 B=1
1 1 D=1 1 1
01
11
C=1
10
Copyright 2007 David Vernon (www.vernon.eu)
f1 = A . B . C . D +A. ( B + C + D) . (B . C . D)
Karnaugh
Maps
AB 00 CD 00 01
A=1
11 10
0 0 0 0
0 0 0 0
0 1 1 1 B=1
1 1 D=1 1 1
01
f1 = A.B + A.C + A.D
11
C=1
10
Copyright 2007 David Vernon (www.vernon.eu)
Karnaugh Maps
Note: This simplification is better than we managed with our hand simplification earlier!!
Copyright 2007 David Vernon (www.vernon.eu)
f1 = A . B . C . D + A.C + A.D Corresponding
Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
f1 = A . B . C . D + A.C + A.D
Corresponding NAND Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
f1 = A . B . C . D + A.C + A.D
Corresponding NAND Digital Circuit
(chill) A (NOT chill) A (rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
Copyright 2007 David Vernon (www.vernon.eu)
f1
X+Y+Z = X.Y.Z
Exercise
Use a truth table, minterms, and a Karnaugh map to simplify the following expression f2 = A . (B + C + D) + A . B . C . D
Copyright 2007 David Vernon (www.vernon.eu)
f2 = A . (B + C + D) + A . B . C . D
Karnaugh Maps
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 f2 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 Minterm m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
Copyright 2007 David Vernon (www.vernon.eu)
f2 = A . (B + C + D) + A . B . C . D
Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
m0 m1 m3 m2
m4 m5 m7 m6
m12 m8 m13 m9 D=1 m15 m11 m14 m10
01
11
C=1
10
B=1
Copyright 2007 David Vernon (www.vernon.eu)
f2 = A . (B + C + D) + A . B . C . D
Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
0 1 1 1
1 1 1 1
1 0 0 0 B=1
0 0 D=1 0 0
01
11
C=1
10
Copyright 2007 David Vernon (www.vernon.eu)
f2 = A . (B + C + D) + A . B . C . D
Karnaugh Maps
AB 00 CD 00 01
A=1
11 10
0 1 1 1
1 1 1 1
1 0 0 0 B=1
0 0 D=1 0 0
01
11
C=1
10
f2 = B.C.D + A.C + A.D
Copyright 2007 David Vernon (www.vernon.eu)
(chill) A (NOT chill) A
f1 = A.B+A.C+A.D
(rash) B (NOT rash) B (bloodshot eyes) C (NOT bloodshot eyes) C (fever) D (NOT fever) D
f1
f2 = B.C.D + A.C + A.D
f2
Copyright 2007 David Vernon (www.vernon.eu)
Simplification of Expressions
Sometimes, a minterm never occurs in a system, i.e., the condition given by that minterm never arises In this instance, we can use either 1 or 0 in the Karnaugh map when simplifying expressions In fact, we use the convention that such conditions are dont careconditions and are signified by X rather than 0/1 We use the value 0 or 1 depending on which leads to the simplest expression
Copyright 2007 David Vernon (www.vernon.eu)
BINARY ARITHMETIC
Binary Addition
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
A digital adder will add just two binary numbers When two binary digits (bits) A and B are added, two results are required:
the sum S the carry C0 to the next place
The circuit to do this is called a Half Adder (HA)
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
A HA B
C0 S
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
Truth Table for addition of two binary digits
A 0 0 1 1
B 0 1 0 1
S 0 1 1 0
C0 0 0 0 1
Copyright 2007 David Vernon (www.vernon.eu)
Half-Adder
From the truth table we see that: S =A.B + A.B = A XOR B C0 = A . B
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
C0
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
A C0
S B
Copyright 2007 David Vernon (www.vernon.eu)
Half Adder
Note that the S output is separated from the inputs by 3 levels of gates
referred to as logical depth of 3
While the C0 output is separated by just 1 level
logical depth of 1
Because of propagation delays, this means that the carry out will be produced before the sum
This may cause problems in some circumstances
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
In order to add together multiple-digit numbers, we need a slightly more complicated circuit
Need to add the two digits and the carry out from the previous or less significant digit Only in the addition of the right-most digits can we ignore this carry
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
1 0 1 1 0
Carry out digits
10110 10011 ------------101001
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
The circuit to add three binary digits (two operands and a carry bit) is called a Full Adder (FA) It can be implemented using two half adders
A B Ci
Ci+1 FA S
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A HA B Ci
Co S
, , HA S Co ,, Co
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
Addition is carried out in two stages
add bits A and B to produce
partial sum S and (the first) intermediate output carry Co
add partial sum S and input carry Ci from previous stage to produce
final sum and (the second) intermediate output carry Co
We then need to combine the intermediate carry bits (they dont have to be added)
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0 0
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A B Ci S Co Co Co S A B A B Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
A few observations The truth table demonstrates why Co = Co + Co Its clear also that S = A B Ci Also, we could obtain a simplified expression for Co from a Karnaugh Map Co = A.B + B.Ci + A.Ci
Copyright 2007 David Vernon (www.vernon.eu)
3-Variable Karnaugh Map
A=1
00 0 01 11 10
C=1
B=1
Copyright 2007 David Vernon (www.vernon.eu)
3-Variable Karnaugh Map
A=1
00 0 01 11 10
0 0
0 1 B=1
1 1
0 1
C=1
Co = A.B + B.Ci + A.Ci
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
So, instead of implementing a full adder as two half adders, we could implement it directly from the gating: S = A B Ci Co = A.B + B.Ci + A.Ci
Copyright 2007 David Vernon (www.vernon.eu)
Full Adder
Irrespective of the implementation of a full adder, we can combine them to add multiple digit binary numbers
Copyright 2007 David Vernon (www.vernon.eu)
4-Bit Binary Adder
S3 Co Full Adder A3 B3 Ci Co
S2 Co
S1 Co
S0
Full Adder A2 B2 Ci
Full Adder A1 B1 Ci
Half Adder A0 B0
Copyright 2007 David Vernon (www.vernon.eu)
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