Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology

with Self-Induced Collapse Write Assist

Daeyeon Kim, Jami Wiedemer, Pramod Kolar, Ayush Shrivastava, Jinal Shah, Satyanand Nalam,
Gwanghyeon Baek, Xiaofei Wang, Zheng Guo, Eric Karl
Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA, E-mail: [email protected]

Abstract diagram and waveforms of SIC. During write operation, the

Exceptionally low minimum operating voltage (VMIN) stacked PMOS transistors between VCC and VCS passively
SRAM arrays have been demonstrated on 22nm FinFET low induce a certain amount of voltage drop at VCS, increasing
power technology (22FFL) [1]. By optimizing an undoped write margin. Compared to TVC and NBL assists, it does not
SRAM transistor and applying industry standard write assist require active circuitry or careful timing between control
techniques, 16Mb array of 0.087μm2 high-density bitcell signals. Improved σVT in 22FFL makes SIC reasonably
(HDC) and 32Mb array of 0.107μm2 high-current bitcell effective in VMIN reduction even for HDC.
(HCC) achieve the 95th percentile VMIN of 505mV and 450mV The array implementation is described in Fig. 8. To
respectively across a temperature range of -10°C to 95°C. A maximize the array efficiency, SIC cell for the stacked PMOS
self-induced collapse (SIC) write assist integrated into the 6-T transistors as well as VCS isolation cell is modified from the
HDC SRAM bitcell array enables 110mV VMIN reduction actual SRAM bitcell – no additional transition space required.
relative to an unassisted array at the 95th percentile with One VCS node is connected to only 30 bitcells to guarantee
negligible power overhead. enough voltage drop at VCS and to minimize power overhead.
The modular integration scheme enables 6-T SRAM to take
Introduction advantage of 2.5-5.5% area overhead of SIC, compared to 3.5-
The ever-increasing necessity of battery-operated mobile 13% area overhead of TVC. Also, it eliminates the necessity
and Internet-of-Things devices continues to emphasize the of device sizing and signal timing optimization in write assist
importance of low voltage operation. 22FFL [1] is introduced circuitry for different-size instances.
to provide a unique combination of low wafer cost and ease of
design, high performance FinFET transistors, ultra-low VMIN and Write Power Reduction with SIC
leakage and ultra-low VMIN for memory and logic circuits. The active (read and write) VMIN distributions of 3.75Mb
Low wafer cost and ease of design is achieved through HDC array are shown in Fig. 9. With SIC, 110mV VMIN
extensive use of single patterning in the metal stack and reduction is achieved compared to no write assist (NOWA) at
simplified design rules. the 95th percentile. The elimination of control signals and
In this paper, the ultra-low VMIN of HDC and HCC arrays active circuitry result in negligible power overhead over
on 22FFL are demonstrated using conventional write assist NOWA, as seen in power measurements at 675mV and 1GHz
techniques. Furthermore, an SIC circuit for 6-T SRAM is (Fig. 10). In contrast to TVC, the local VCS in SIC is only
introduced to provide VMIN improvement with minimal power connected to 30 bitcells instead of the full column, and only
overhead and significantly reduced design complexity. columns containing a low write margin bitcell will experience
noticeable self-induced collapse, so the dynamic power
SRAM Bitcells and VMIN with Conventional Write Assist consumption is minimized. For even lower VMIN operation,
Fig. 1 shows the planar TEM images of HDC and HCC. wide-pulse TVC enables 115mV VMIN reduction at the
The fin ratio of 1:1:1 (PU:PG:PD) is used in HDC to minimize expense of additional 65% write power overhead. The trade-
bitcell footprint while HCC uses a larger PG and PD at 1:2:2 off between the 95th percentile write power and VMIN is
to lower VMIN and to increase performance. Pulsed transient summarized in Fig. 11. SIC provides an attractive tradeoff by
voltage collapse (TVC) [2] (Fig. 2) and negative bit-line lowering VMIN by 110mV with negligible power overhead,
(NBL) [3] (Fig. 3) write assist techniques are utilized in HDC limited design complexity and more uniform behavior across
and HCC respectively to improve write margin at low different-size instances.
voltages. Fig. 4 shows active (read and write) and retention Fig. 12 contains the shmoo of NOWA, SIC, and wide-
VMIN distributions of 16Mb of HDC and 32Mb HCC arrays. pulse TVC. A 2064x68 2-cycle latency HDC SRAM array
HDC array shows the worst-case VMIN distribution of 505mV with TVC achieves 2.1GHz at 720mV/-10C. At 720mV, SIC
at the 95th percentile and 430mV at median. HCC array provides 12% better performance than NOWA. The die
demonstrates the VMIN of 450mV and 415mV at the 95th micrograph is shown in Fig. 13.
percentile and at median respectively.
One of the key transistor features which enables Conclusion
exceptionally low VMIN is VT targeting based on gate length We demonstrated the 95th percentile VMIN at -10°C/95°C of
and work function, which enables improved random VT 505mV and 450mV of 16Mb HDC and 32Mb HCC arrays
variation (σVT) [1]. The measured σVT of 13mV/14mV for respectively. Using SIC, 110mV of VMIN reduction with
single fin NMOS/PMOS transistors is a 2.5X improvement negligible power overhead relative to an unassisted array is
over the previous 22nm [4] (Fig. 5). demonstrated on an HDC array.
Self-Induced Collapse (SIC) Write Assist References
Even though TVC and NBL have been widely used to [1] B. Sell, et al., IEDM, pp. 685-688, Dec. 2017
lower VMIN, they lead to power [2] and area overheads. Area [2] E. Karl, et al., JSSC, pp. 222-229, Jan. 2016
overhead is significant for small instances (Fig. 6) due to [3] E. Karl, et al., IEDM, pp. 561-564, Dec. 2012
[4] S. Natarajan, et al., IEDM, pp. 71-73, Dec. 2014
fixed-size active write assist. SIC, which has been used for [5] M. Yuffe, et al., JSSC, pp. 194-205, Jan. 2012
hierarchical 8-T SRAM [5-7], is introduced for 6-T SRAM to [6] J. Kulkarni, et al., ISSCC, pp. 234-235, Feb. 2012
mitigate area and power overheads. Fig. 7 shows the circuit [7] K. Koo, et al., VLSIC, pp. 266-267, June 2015

978-1-5386-4218-4/18/$31.00 ©2018 IEEE 2018 Symposium on VLSI Technology Digest of Technical Papers 151
Authorized licensed use limited to: Dayananda Sagar University. Downloaded on September 06,2021 at 07:19:48 UTC from IEEE Xplore. Restrictions apply.
 VCC
VCC
PG1 PU2 PD2 PG1 PU2 PD2
VCC
6-T SRAM Cells
PD1 PU1 PG2 PD1 PU1 PG2 WAKE
TVCPULSE_B BIAS_B[1:0]
BL BL#
0.087μm2 HDC 0.107μm2 HCC
WL
Fig. 1 Planar TEM Images of Bitcells WR Driver VCS
BL# BL
VCS PU1 PU2
NBLVSS PG1 N1 PG2
N0
6-T SRAM Cells NBLPULSE PD1 PD2
NBLCAP
505mV
6-T SRAM Cells
Retention

Goal @ 95%
Active VMIN
95°C

VCC VCC VCC

Retention

Active 95°C

VCS VCS VCS

Active -10°C
-10°C

WL VSS WL VSS WL VSS

VCC
HDC BIAS_B[1:0] BL
VCC
N0
VCC

16Mb
TVCPULSE_B VSS BL# VSS N1 VSS
200 300 400 500 600 700
VMIN (mV) Tunable Pulsewidth
450mV Fig. 2 TVC Circuit Diagram Fig. 3 NBL Circuit Diagram Fig. 7 SIC Circuit Diagram
and Waveforms [2] and Waveforms [3] and Waveforms
Active 95°C
Active -10°C
Retention

Goal @ 95%
Active VMIN
95°C

Retention

Increased area
Single Device σVT (mV)
-10°C

Area Overhead (%)

overhead of TVC for
HCC 2.5X small instances
32Mb reduction

200 300 400 500 600 700

VMIN (mV)
Fig. 4 Measured VMIN Distributions of 16Mb HDC
and 32Mb HCC with Conventional Write Assist
32nm 22nm 22nm 14nm
Edge Cell (22FFL)
30-bit Bitcell Unit
This Work # of Rows
VCS[0]

VCC VCS
6-T SRAM Bitcells Fig. 5 Measured Random Fig. 6 Area Overhead
Variation Comparison [4] of Write Assist Circuits
SIC Cell
SIC Cell
110mV
SIC
VCS[1]

VCS Isolation Cell 6-T SRAM Bitcells 225mV NOWA 0.60X TVC (Wide)
WL[0] VCS TVC (Wide) SIC/NOWA
VCS
VCS Isolation Cell
BL# BL
VCS Isolation Cell 1 TVC SIC
SIC TVC
(Wide) TVC
VCS[2]

30
TVC
NOWA (Narrow)
6-T SRAM Bitcells (Mid) (Narrow) TVC
NOWA
6-T SRAM Bitcell
TVC (Wide)
SIC Cell 1
VCS
SIC Cell (Mid)
WL[...]
6-T SRAM Bitcells

VCS
VCS VCC
HDC 3.75Mb
SIC Cell HDC 3.75Mb 1GHz/-10°C
SIC Cell
Low Freq. /-10°C 675mV
VCS[n-1]

6-T SRAM Bitcells VMIN (A.U.) Write Power (A.U.)

SIC Cell
Fig. 9 Measured Active VMIN Fig. 10 Measured Write Power
Edge Cell
Distrubutions Distributions
Fig. 8 SIC Array Implementation

1000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

NOWA
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

HDC
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3
1
3.75Mb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3
Supply Voltage (mV)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3

TVC 900
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
TVC (Wide)

110mV -10°C
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3

(Narrow)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 0
VMIN (A.U.)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0 0
NOWA

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 0 0

800
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 3 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 0 0 0 0 0
SIC

1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 3 0 0 0 0 0 0

720mv
1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0 0 0 0 0 0 0

SIC
1 1 1 1 1 1 1 1 1 1 1 2 3 3 3 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 2 2 3 3 0 0 0 0 0 0 0 0 0

700
1 1 1 1 1 1 1 1 2 2 2 3 3 3 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 2 2 2 3 3 3 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 2 2 2 3 3 3 0 0 0 0 0 0 0 0 0 0 0

TVC
1 1 1 1 1 2 2 2 2 3 3 3 0 0 0 0 0 0 0 0 0 0 0

TVC 1
1
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
2
2
3
3
3
2
3
3
3
3
3
3
3
3
0
3
3
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

(Mid) (Wide)
1.7GHz
1.9GHz
2.1GHz

2 2 2 2 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

600
2 2 2 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0.60X 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

500
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1.0 1.5 2.0 2.5 3.0

Normalized Write Power Frequency (GHz)
Fig. 11 Measured Write Power and Active VMIN Fig. 13 Die Micrograph
Fig. 12 Measured Voltage-Frequency Shmoo
Trade-off at the 95th Percentile

2018 Symposium on VLSI Technology Digest of Technical Papers 152

Authorized licensed use limited to: Dayananda Sagar University. Downloaded on September 06,2021 at 07:19:48 UTC from IEEE Xplore. Restrictions apply.