Cover

T6573/T6563/T6533

VLSI TEST SYSTEM

PRODUCT DESCRIPTION

MANUAL NUMBER 8350430-06

Applicable Systems
T6573
T6563
T6533

C 2000 ADVANTEST CORPORATION First printing September 29, 2000

All rights reserved. Printed in Japan
 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

PREFACE
PREFACE
Viewpoint is a trademark of ADVANTEST Corporation.

Sun, Sun Microsystems, Sun logo, Solaris and Ultra are trademarks or registered trademarks of Sun
Microsystems, Inc. in the United States and other countries.

All SPARC trademarks are used under license of SPARC International, Inc. and are also trademarks or
registered trademarks of Sun Microsystems, Inc. in the United States and other countries. Products
bearing SPARC trademarks are based on an architecture developed by Sun Microsystems, Inc.

VxWorks is a registered trademark of Wind River Systems, Inc.

UNIX is a registered trademark in the United States and other countries, licensed exclusively through
The Open Group.

All other marks referenced herein are trademarks or registered trademarks of their respective owners.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

RECORD OF REVISIONS

Manual Manual
Date Remarks Date Remarks
Rev Rev

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

TABLE OF CONTENTS
TABLE OF CONTENTS
1. INTRODUCTION ................................................................................. 1-1
1.1 T6573, T6563, and T6533 VLSI Test Systems ....................................... 1-1

2. SYSTEM EXTERNAL VIEW AND HARDWARE

CONFIGURATION .............................................................................. 2-1
2.1 System External View ............................................................................. 2-1
2.2 Hardware Configuration .......................................................................... 2-2

3. T6573, T6563, AND T6533 FEATURES ....................................... 3-1

3.1 Reducing Testing Costs .......................................................................... 3-1
3.1.1 Reducing Testing Costs through Compactness,
Space-Saving Features, and Low Power Consumption ................... 3-1
3.1.2 Reducing Testing Costs by Improving Throughput ........................... 3-1
3.1.3 Reducing Testing Costs by Improving Productivity ........................... 3-1
3.1.4 High Reliability and Maintainability ................................................... 3-2
3.2 Characteristics of Device Tests .............................................................. 3-3
3.2.1 PTMUX and PMUX Functions for At-Speed Testing ........................ 3-3
3.2.2 Field Upgrading Compatible with Increased Speeds
of Target Devices .............................................................................. 3-3
3.2.3 Timing Calibration to Assure Timing Accuracy ................................. 3-3
3.2.4 SQPG Applicable to Huge Test Pattern Program Files .................... 3-3
3.2.5 Pin Electronics Compatible with High-Speed,
Small Amplitude Interface ................................................................. 3-3
3.2.6 Timing Resolution That Enables High-Accuracy Tests ..................... 3-4
3.2.7 Timing Flexibility That Shortens TAT ................................................ 3-4
3.2.8 Dynamic Pin Scramble Function Applicable to Various Packages ... 3-4
3.2.9 ALPG Option for Embedded Memory Test ....................................... 3-5
3.2.10 AFM Option for Fail Analysis of Embedded Memory ........................ 3-5
3.2.11 SCPG Option for Scan Test .............................................................. 3-5
3.2.12 Analog Option for Analog Section Test ............................................. 3-5
3.2.13 Iddq Option ....................................................................................... 3-5
3.3 Performance Board Types ...................................................................... 3-6

4. RATE GENERATOR .......................................................................... 4-1

5. SQPG THAT GENERATES LARGE-SIZE PATTERN DATA ... 5-1

5.1 Outline ..................................................................................................... 5-1
5.2 DFM Used to Store Failure Information .................................................. 5-2
5.3 Match Function ....................................................................................... 5-3
5.3.1 Match Function ................................................................................. 5-3
5.3.2 Match Types ..................................................................................... 5-3

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Table of Contents

5.3.3 Match Function Operation Modes ..................................................... 5-4

5.4 Register Loop Function ........................................................................... 5-5
5.5 Bump Function ........................................................................................ 5-6

6. FRAME PROCESSOR (FP) FOR INPUT WAVEFORM

GENERATION FOR DUTS AND OUTPUT COMPARISONS .. 6-1
6.1 Outline ..................................................................................................... 6-1
6.2 Timing Edge Functions ........................................................................... 6-2
6.3 DUT Output Comparison ........................................................................ 6-3
6.4 Pattern Multiplex Function (PTMUX) ...................................................... 6-5
6.5 Multiple Clock Function (MCLK) ............................................................. 6-7
6.6 Frequency Measurement Function ......................................................... 6-7

7. PIN ELECTRONICS ........................................................................... 7-1

7.1 Overview ................................................................................................. 7-1
7.2 Driver ...................................................................................................... 7-1
7.3 Comparator ............................................................................................. 7-2
7.4 Programmable Load ............................................................................... 7-2
7.5 Dynamic Clamp (DCLP) .......................................................................... 7-2
7.6 On-the-fly Terminator .............................................................................. 7-3
7.7 Overvoltage Detection Circuit ................................................................. 7-3
7.8 Pin Multiplexing (PMUX) ......................................................................... 7-4

8. TWO DC PARAMETRIC TEST UNITS (MDC, UDC) ................. 8-1

8.1 Outline ..................................................................................................... 8-1
8.2 Multi DC Unit (MDC) ............................................................................... 8-1
8.3 Universal DC Unit (UDC) ........................................................................ 8-1

9. DEVICE POWER SUPPLY ............................................................... 9-1

9.1 Overview ................................................................................................. 9-1
9.2 Current Measurement Function .............................................................. 9-3
9.3 Voltage Source Voltage Measurement Function .................................... 9-3
9.4 Parallel Operation Function .................................................................... 9-3
9.5 Average Current Measurement Function ................................................ 9-3
9.6 Programmable Slew Rate ....................................................................... 9-4
9.7 Alarm Functions ...................................................................................... 9-4

10. DUT INTERFACE ................................................................................ 10-1

10.1 Test Head ............................................................................................... 10-1
10.2 HIFIX and Performance Board ................................................................ 10-2
10.3 HIFIX Resources ..................................................................................... 10-3

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Table of Contents

11. OPTION PG .......................................................................................... 11-1

11.1 ALPG (OPTION): GENERATING COMPLEX MEMORY PATTERNS ... 11-1
11.1.1 Overview ........................................................................................... 11-1
11.1.2 Connection to any I/O Pin from the PDS .......................................... 11-2
11.1.3 Address Descramble Function .......................................................... 11-2
11.1.4 Auto Refresh Function ...................................................................... 11-2
11.1.5 Cycle Shift Function .......................................................................... 11-3
11.1.6 Regional Inversion Function (ARIRAM) ............................................ 11-3
11.1.7 Address Fail Memory AFM (Option) ................................................. 11-3
11.2 SCPG (OPTION) FOR GENERATING SCAN PATTERNS .................... 11-4
11.2.1 Overview ........................................................................................... 11-4
11.2.2 Pattern Data Assignment to a Pin by the Programmable Data
Selector (PDS) .................................................................................. 11-5

12. A/D AND D/A CONVERTER MEASUREMENT OPTION .......... 12-1

12.1 Analog Waveform Generation Function for A/D Converter Measurement
(HLFG function for converters) ............................................................... 12-1
12.2 Output Data Capture for A/D Converter (DCAP function) ....................... 12-1
12.3 Data Generator for D/A Converter (SCPG DAW function) ...................... 12-1
12.4 Analog Waveform Capture for D/A Converter
(HLFD Function for Converter) .............................................................. 12-1
12.5 Sampling Clock Controller (LSYNC function) ......................................... 12-2
12.6 Analog Reference Supply (VREF function) ............................................. 12-2
12.7 MTX function ........................................................................................... 12-2

13. MULTIPLE DEVICE PARALLEL TEST FUNCTION ................... 13-1

14. HRS FOR HIGH-SPEED PATTERN TRANSFER (OPTION) ... 14-1

15. COMPUTING ARCHITECTURE ...................................................... 15-1

15.1 Overview ................................................................................................. 15-1

16. OPERATING ENVIRONMENT ........................................................ 16-1

16.1 Using the NRT Processor ....................................................................... 16-1
16.2 Using the Control Panel .......................................................................... 16-2
16.3 Batch Operation (Option) Using TIM Software ....................................... 16-3

17. Viewpoint SOFTWARE ...................................................................... 17-1

17.1 Overview ................................................................................................. 17-1
17.2 Viewpoint Programming Language and Test Execution Environments .. 17-2
17.3 Tools ....................................................................................................... 17-3
17.3.1 Siteseer ............................................................................................. 17-3

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Table of Contents

17.3.2 Viewpoint Console ............................................................................ 17-4

17.3.3 SystemViewer ................................................................................... 17-5
17.3.4 Pattern Viewer .................................................................................. 17-6
17.3.5 Logic Analyzer Tool .......................................................................... 17-7
17.3.6 Oscilloscope Tool .............................................................................. 17-8
17.3.7 Shmoo2 ............................................................................................. 17-9
17.3.8 DataScan .......................................................................................... 17-10
17.3.9 Margin ............................................................................................... 17-11
17.3.10 Fbmap ............................................................................................. 17-12
17.3.11 ALGP Tool ...................................................................................... 17-12
17.3.12 Mtrace ............................................................................................. 17-12
17.3.13 Wavescope ..................................................................................... 17-12
17.3.14 Wafer Map ...................................................................................... 17-13
17.3.15 Summary ......................................................................................... 17-13
17.3.16 TDL Debugger ................................................................................ 17-13
17.3.17 Mask Tool ....................................................................................... 17-13
17.4 Linking of Tools ....................................................................................... 17-14
17.5 Viewpoint Online Manual ........................................................................ 17-15
17.6 Vsim (Option) .......................................................................................... 17-15

18. INSTALLATION ................................................................................... 18-1

18.1 Operating Environment ........................................................................... 18-1
18.2 Calibration ............................................................................................... 18-1
18.3 Power Supply .......................................................................................... 18-2
18.3.1 Power Supply Requirements ............................................................ 18-2
18.3.2 Power Supply Connection ................................................................. 18-2
18.3.3 Power Consumption .......................................................................... 18-3
18.4 Compressed Air Supply .......................................................................... 18-3
18.4.1 Compressed Air Requirements ......................................................... 18-3
18.4.2 Plumbing ........................................................................................... 18-3
18.5 Locations at Which AC Power and Compressed Air are Supplied ......... 18-4
18.6 Heat Consumption and Ventilation in the Test System ........................... 18-5
18.6.1 Heat Consumption ............................................................................ 18-5
18.6.2 Ventilation ......................................................................................... 18-5
18.6.3 Fan Location ..................................................................................... 18-6
18.7 Floor Plan ................................................................................................ 18-8
18.8 Weight ..................................................................................................... 18-18
18.9 Earthquake Protection Measures ............................................................ 18-22

19. REPLACEMENT OF LIMITED LIFE PARTS ................................ 19-1

20. LIMITED WARRANTY AND CUSTOMER SERVICE ................. 20-1

20.1 Limited Warranty ..................................................................................... 20-1

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Table of Contents

20.2 Customer Service Description ................................................................ 20-3

21. ACCEPTANCE TEST AND INSTALLATION ................................ 21-1

21.1 Acceptance Test ..................................................................................... 21-1
21.2 Installation ............................................................................................... 21-1

22. SPECIFICATIONS .............................................................................. 22-1

22.1 System Specifications ............................................................................. 22-1
22.2 Timing Specifications .............................................................................. 22-3
22.3 Driver Specifications ............................................................................... 22-4
22.4 Comparator Specifications ...................................................................... 22-5
22.5 Terminator Specifications ....................................................................... 22-6
22.6 Programmable Load Specifications ........................................................ 22-6
22.7 Dynamic Clamp Specifications ............................................................... 22-6
22.8 Multi-DC Unit Specifications ................................................................... 22-7
22.8.1 Voltage Source Current Measurement (VSIM) ................................. 22-7
22.8.2 Current Source Voltage Measurement (ISVM) ................................. 22-8
22.8.3 Voltage Measurement (MVM) ........................................................... 22-9
22.9 Universal DC Unit ................................................................................... 22-10
22.9.1 Voltage Source Current Measurement (VSIM)
during Dedicated Terminal Output .................................................... 22-10
22.9.2 Current Source Voltage Measurement (ISVM)
during Dedicated Terminal Output .................................................... 22-12
22.9.3 Voltage Measurement (MVM) during Dedicated Terminal Output .... 22-14
22.9.4 Voltage Source Current Measurement (VSIM)
when MDC Interruption ..................................................................... 22-15
22.9.5 Current Source Voltage Measurement (ISVM)
during MDC Interruption .................................................................... 22-16
22.9.6 Voltage Source Current Measurement (VSIM)
when Connected to Converters Option ............................................. 22-17
22.9.7 Current Source Voltage Measurement (ISVM)
when Connected to Converters Option ............................................. 22-18
22.10 Device Specifications ............................................................................ 22-19
22.10.1 Voltage Source Current Measurement (VSIM) ............................... 22-19
22.10.2 Current Measurement during Parallel Operation (VSIM) ................ 22-20
22.10.3 Voltage Source Voltage Measurement (VSVM) .............................. 22-20
22.10.4 Mean Current Measurement ........................................................... 22-20
22.10.5 Programmable Slew Rate ............................................................... 22-21
22.10.6 Overshoot and Undershoot ............................................................. 22-21
22.10.7 Load Fluctuation Characteristics ..................................................... 22-21
22.11 SQPG Specifications ............................................................................ 22-22
22.12 ALPG Specifications (Option) ............................................................... 22-22
22.13 AFM Specifications (Option) ................................................................. 22-22

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Table of Contents

22.14 SCPG Specifications (Option) ............................................................... 22-23

22.14.1 Scan Pattern Generation ................................................................ 22-23
22.14.2 DAW Pattern Generation ................................................................ 22-23
22.15 Frequency Measurement Specification ................................................. 22-24

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

LIST OF ILLUSTRATIONS

No. Title Page

2-1 External View ...................................................................................................... 2-1

2-2 Block Diagram of the System .............................................................................. 2-2

3-1 Pin Scramble ....................................................................................................... 3-4

5-1 SQPG Block Diagram ......................................................................................... 5-1

5-2 Match Types ....................................................................................................... 5-3
5-3 Fixed Cycle Match Mode .................................................................................... 5-4
5-4 Fixed Delay Match Mode .................................................................................... 5-4
5-5 Register Loop Operation ..................................................................................... 5-5
5-6 Changing the Device Power Supply Voltage Using the Bump Function ............. 5-6

6-1 Block Diagram of Frame Processor (FP) ............................................................ 6-1

6-2 Standard Uses of Timing Edges ......................................................................... 6-2
6-3 Comparison with an Edge Strobe ....................................................................... 6-3
6-4 Comparison with a Window Strobe ..................................................................... 6-3
6-5 Output Comparison in Normal Mode .................................................................. 6-3
6-6 Output Comparison in Double-speed Mode ........................................................ 6-3
6-7 Output Comparison in Transition Mode .............................................................. 6-3
6-8 Timing Edge Functions When Pattern Multiplex Function is Used ..................... 6-5
6-9 Example of Combined Use of Pattern Multiplex Function
and Pin Multiplex Function .................................................................................. 6-6
6-10 Example of Multiple Clocks ................................................................................. 6-7

7-1 Pin Electronics Configuration .............................................................................. 7-1

7-2 Using Dynamic Clamp ........................................................................................ 7-2
7-3 On-the-fly Terminator Operation ......................................................................... 7-3
7-4 Operation when PMUX is Used .......................................................................... 7-4
7-5 Wiring in T66 Mode for PMUX ............................................................................ 7-5
7-6 Wiring in T33 Mode for PMUX ............................................................................ 7-5

8-1 DC Parametric Test Unit Controller .................................................................... 8-2

9-1 DPS Connection when 512pogoHIFIX is Used ................................................... 9-1

9-2 DPS Connection when 512ZIFHIFIX is Used ..................................................... 9-2
9-3 DPS Connection when 512AV2HIFIX is Used .................................................... 9-2
9-4 Control of Slew Rate ........................................................................................... 9-4

10-1 Connecting the HIFIX and the Performance Board ............................................ 10-2

11-1 Pattern Generation by the ALPG ........................................................................ 11-1

11-2 Scan Test Pattern Generation ............................................................................ 11-4
11-3 Concept of SCPG Output .................................................................................... 11-4

14-1 Pattern Transfer by HRS ..................................................................................... 14-1

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List of Illustrations

No. Title Page

15-1 TC4 Computing Architecture ............................................................................... 15-1

15-2 TC7 Computing System Architecture .................................................................. 15-3

16-1 Batch Operations from a PC ............................................................................... 16-3

16-2 Batch Operation from the Prober ........................................................................ 16-4

17-1 Viewpoint Software ............................................................................................. 17-1

17-2 Test Program Execution Environment ................................................................ 17-2
17-3 Siteseer ............................................................................................................... 17-3
17-4 Viewpoint Console .............................................................................................. 17-4
17-5 SystemViewer ..................................................................................................... 17-5
17-6 Pattern Viewer .................................................................................................... 17-6
17-7 Logic Analyzer Tool ............................................................................................ 17-7
17-8 Oscilloscope Tool ................................................................................................ 17-8
17-9 Shmoo2 ............................................................................................................... 17-9
17-10 DataScan Window Layout ................................................................................... 17-10
17-11 Margin ................................................................................................................. 17-11
17-12 Fbmap ................................................................................................................. 17-12
17-13 Wafer Map .......................................................................................................... 17-13
17-14 Inter-tool Link from Patview ................................................................................ 17-14

18-1 Power Supply Connection ................................................................................... 18-2

18-2 Air Hose Connection ........................................................................................... 18-3
18-3 Locations where AC Power Supply and Air Hose are Connected (REAR View) 18-4
18-4 Mainframe Fan Location ..................................................................................... 18-6
18-5 Test Head Fan Location ...................................................................................... 18-7
18-6 Floor Plan for Manual Test (Built-in Monitor) ...................................................... 18-9
18-7 Floor Plan for Manual Test (External Monitor) .................................................... 18-10
18-8 Floor Plan for Manual Test (External Monitor TC7 Installation) .......................... 18-11
18-9 Floor Plan for Handler (M4541A) Connection (Built-in Monitor) ......................... 18-12
18-10 Floor Plan for Handler (M4541A) Connection (External Monitor) ....................... 18-13
18-11 Floor Plan for Handler (M4541A) Connection
(External Monitor TC7 Installation) ..................................................................... 18-14
18-12 Floor Plan for Wafer Prober Connection (Built-in Monitor) ................................. 18-15
18-13 Floor Plan for Wafer Prober Connection (External Monitor) ............................... 18-16
18-14 Floor Plan for Wafer Prober Connection (External Monitor TC7 Installation) ..... 18-17
18-15 Location of Mainframe Jacks .............................................................................. 18-19
18-16 Location of Test Head Jacks ............................................................................... 18-20
18-17 Location of Monitor Desk Jacks .......................................................................... 18-20
18-18 Location of the External TC7 Expansion Frame Jacks ....................................... 18-21
18-19 Location of Earthquake Protection Equipment .................................................... 18-23
18-20 Location of Earthquake Protection Equipment
(External Monitor TC7 Installation) ..................................................................... 18-24

22-1 When RESET is Inserted between SET and SET of Different Timing Edges ..... 22-3
22-2 When SET is Inserted between RESET and RESET of Different Timing Edges 22-3
22-3 Driver Loading Conditions ................................................................................... 22-4

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

LIST OF TABLES

No. Title Page

4-1 Range of the Test Rate ....................................................................................... 4-1

5-1 Pattern Capacity of SQPG .................................................................................. 5-1

5-2 DFM Capacity ..................................................................................................... 5-2

6-1 Standard Timing Edge Functions ........................................................................ 6-2

6-2 Detectable DUT Output Status ........................................................................... 6-4
6-3 Timing Edge Functions When Pattern Multiplex Function is Used ..................... 6-5

8-1 Correspondence between DC Parametric Test Units and Pins .......................... 8-3

10-1 Signals and Power Supply on Test Head ........................................................... 10-1

10-2 Performance Board and HIFIX ............................................................................ 10-2
10-3 Available Resources for Each Type of HIFIX ...................................................... 10-3
10-4 Specified Wiring Length and I/O tpd for Each Performance Board ..................... 10-3

11-1 ALPG Specifications ........................................................................................... 11-2

11-2 AFM Specifications ............................................................................................ 11-3

13-1 Tester Resource Assignments when 64 Pins are Assigned to Each DUT
(512-pin System) ................................................................................................. 13-1
13-2 Tester Resource Assignments when 128 Pins are Assigned to Each DUT
(512-pin System) ................................................................................................. 13-1
13-3 Tester Resource Assignments when 256 Pins are Assigned to Each DUT
(512-pin System) ................................................................................................. 13-2
13-4 Tester Resource Assignments when 64 Pins are Assigned to Each DUT
(256-pin System) ................................................................................................. 13-2
13-5 Tester Resource Assignments when 128 Pins are Assigned to Each DUT
(256-pin System) ................................................................................................. 13-2

15-1 TC4 Configuration ............................................................................................... 15-2

15-2 TC7 Configuration ............................................................................................... 15-3

18-1 Operating Environment ....................................................................................... 18-1

18-2 Power Supply Requirements .............................................................................. 18-2
18-3 Power Consumption ............................................................................................ 18-3
18-4 Compressed Air Requirements ........................................................................... 18-3
18-5 Heat Consumption .............................................................................................. 18-5
18-6 Ventilation Airflow ............................................................................................... 18-5
18-7 Range of Movement ............................................................................................ 18-8
18-8 Weight of T6573, T6563, and T6533 Components ............................................. 18-18

19-1 Limited Life Parts ................................................................................................ 19-1

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

1. INTRODUCTION

1. INTRODUCTION
The recent trend in process refinement has been greater integration, more advanced functions, and
faster devices. Testing such devices requires a very large test pattern program file, analysis of
many embedded memory and analog unit functions, and a high level of test precision. These re-
quirements increase testing costs and test times.
Test systems for these devices must therefore incorporate higher performance, advanced func-
tions, and lower testing costs.
To meet these requirements, ADVANTEST offers various test systems optimized for testing at
each stage from design and evaluation to mass production.
The systems used for design and performance evaluations and the systems used for mass produc-
tion provide a test environment using a common platform and reduce overall testing costs.

1.1 T6573, T6563, and T6533 VLSI Test Systems

The T6500 series test systems are mass production test systems. They have compatible device
test programs and performance boards (*) and share common operating environments with the up-
per-level T6682 and T6672 models, enabling a smooth transition to mass production.
ADVANTEST offers the following three T6500 series models running at different basic frequencies:
• T6573 (125 MHz)
• T6563 (62.5 MHz)
• T6533 (31.25 MHz)
The basic frequency of the T6563 and T6533 can be easily upgraded up to 125 MHz.
As mass production test systems, the T6500 series has the following cost-reducing features:
(1) Compact, space-saving design for efficient use of floor space
(2) Low power consumption for reducing operating costs
(3) Improved parallel test function for reducing testing cost per device
(4) Low prices
(5) Improved MTBF
(6) High performance
• Maximum test rate: 125 MHz (T6573)
• Overall timing accuracy: ±500 ps
• High-capacity pattern memory: 64 megawords (option)
(7) Extensive options for measurement with various functions
• Analog test option
• Scan test option
• Memory test option

*:Common functions are compatible.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

2. SYSTEM EXTERNAL VIEW AND HARDWARE CONFIGURATION

2. SYSTEM EXTERNAL VIEW AND HARDWARE CONFIGURATION

2.1 System External View

Figure 2-1 shows external view of our test system.

Figure 2-1 External View

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

2.2 Hardware Configuration

2.2 Hardware Configuration

Figure 2-2 shows a block diagram of the test system.

SQPG : Sequential Pattern Generator DPS : Device Power Supply

TTB : Truth Table Buffer UDC : Universal DC unit
DFM : Data Fail Memory MDC : Multi DC unit
ALPG : Algorithmic Pattern Generator
SCPG : Scan Pattern Generator
PDS : Programmable Data Selector

Figure 2-2 Block Diagram of the System

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3. T6573, T6563, AND T6533 FEATURES

3. T6573, T6563, AND T6533 FEATURES

3.1 Reducing Testing Costs

3.1.1 Reducing Testing Costs through Compactness, Space-Saving Features,
and Low Power Consumption
The T6573, T6563, and T6533 implement high-density packaging with ASIC devices for the lat-
est processes, reducing the number of parts (50% compared with the T6672), system size, and
power consumption.
Mounting most of the measuring hardware on the test head saves a lot of space and eliminates
the need for some test head cabling.
As a result, floor space is more efficiently used and operating costs are lowered, reducing overall
testing costs.

3.1.2 Reducing Testing Costs by Improving Throughput

To improve throughput, the T6573, T6563, and T6533 enable parallel testing of multiple devices.
A 512-pin system can test up to eight devices simultaneously, and a 256-pin system can test up
to four devices. Up to four devices can also be tested simultaneously in A/D and D/A converter
tests.

3.1.3 Reducing Testing Costs by Improving Productivity

The manufacture of a variety of devices in small lots requires much time because a changeover
is required for each device. The T6573, T6563, and T6533 shorten the changeover time by using
the following functions.

(1) Using TIM for device changeover batch processing

The test integration manager (TIM) is optional software that improves operability on the
production line. With TIM, an operator can batch device setups and then switch to a new
device by simply using the prober. Improved operability eliminates operating errors and
lessens the time for device type changeover.

(2) High-speed pattern program transfer by HRS

The development of devices with higher levels of integration and advanced functions re-
quires huge pattern programs. Much time is required to transfer a huge pattern program file
from the host computer to the pattern generator over a network. Even the time required for
transferring a pattern program file from a local disk in each test system does not meet the
user requirements.
In the manufacture of a variety of devices in small lots, the pattern program file transfer time
reduces productivity because it is contained in the changeover time for each device.
The T6573, T6563, and T6533 provide the high-speed reload server (HRS) option to solve
this problem. The HRS is a pattern program file server that interfaces with the pattern gen-
erator of the test system over a dedicated high-speed bus that operates at speeds up to 40
megabytes per second.
Transferring mass pattern program files efficiently using HRS can shorten the time required
for device changeover.

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3.1 Reducing Testing Costs

3.1.4 High Reliability and Maintainability

T6500 series test systems have an improved MTBF (Mean Time Between Failure) which is made
possible by highly reliable designs and advanced manufacturing technology (such as reduction
of number of parts and PCBs and usage of semiconductor relays for Pin electronics).
In addition, these test systems have excellent maintainability because the diagnostic program
can locate faulty boards and use many compatible boards.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3.2 Characteristics of Device Tests

3.2 Characteristics of Device Tests

3.2.1 PTMUX and PMUX Functions for At-Speed Testing
Based on the at-speed concept by which tests are conducted at the speed under actual operating
conditions, the T6573, T6563, and T6533 provide functions that test devices at a frequency (data
rate) two or four times as fast as the basic operating frequency of the system. The functions are
the pattern multiplex (PTMUX) and pin multiplex (PMUX) functions. Each function can be used
to run a test at twice the basic frequency.
If the functions are used together, a test can be executed at four times the basic frequency.

3.2.2 Field Upgrading Compatible with Increased Speeds of Target Devices

Replacement of the built-in board upgrades the basic frequency of the T6563 and the T6533 to
a maximum of 125 MHz. As a result, if the device operating frequencies increase, the test system
can test the device by simply upgrading the boards.

3.2.3 Timing Calibration to Assure Timing Accuracy

Timing calibration assures driver skew (±200 ps), comparator skew (±200 ps), and overall timing
accuracy (±500 ps) to perform stable testing. In addition, TDR calibration minimizes wiring delay
errors on the performance board to ensure higher-accuracy testing.

3.2.4 SQPG Applicable to Huge Test Pattern Program Files

High-capacity pattern memory is required for testing high-performance microprocessors be-
cause a huge test pattern program is used.
As standard, the sequential pattern generator (SQPG) uses pattern memory of 16 megawords.
A pattern memory of 64 megawords is also provided.
The SQPG therefore can store a huge test pattern program without rewriting the pattern memory.
This improves device test throughput.
In addition, when the register loop function is used, a functional test pattern program can be used
as is for dynamic power current measurements.

3.2.5 Pin Electronics Compatible with High-Speed, Small Amplitude Interface

The pin electronics satisfies CMOS, BiCMOS, and ECL process test conditions. Furthermore,
the driver, with a minimum amplitude of 200 mV, supports small amplitude bus interfaces such
as GTL, CTT, LVDS, and IEEE 1394.

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3.2 Characteristics of Device Tests

3.2.6 Timing Resolution That Enables High-Accuracy Tests

The timing edge can be set at a resolution of 31.25 ps even when the timing is changed on the
fly. This high-resolution timing edge results in evaluation at a high level of timing accuracy and
an accurate acceptance check during mass production. An AC parametric test can test devices
with a resolution of 8 ps.

3.2.7 Timing Flexibility That Shortens TAT

A flexible frame processor can easily establish a link with a simulation. The frame processor gen-
erates waveforms by combining six timing edges for each pin, a test vector of 3 bits per pin, and
up to 32 timing sets.
The timing generator has a function that switches up to 32 timing sets on the fly and can therefore
easily change the timing only for the test cycles being analyzed. This function greatly shortens
the turn around time (TAT) in device development and implements high defect detection rates in
mass production.

3.2.8 Dynamic Pin Scramble Function Applicable to Various Packages

The pin scramble function assigns pattern data and tester pins as desired. When the pattern pro-
gram file is loaded, pattern data and tester pins are assigned according to the pin assignment
information of the device pins and tester pins specified by the test plan program.
With this function, a common pattern program file can be used for testing a device having multiple
packages simply by changing the pin assignment information in the test program.

Pin scramble
(specified in a TDL
program)

Package A Package B Package C

Figure 3-1 Pin Scramble

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3.2 Characteristics of Device Tests

3.2.9 ALPG Option for Embedded Memory Test

The trend in high-performance microprocessors is toward higher-capacity and faster embedded
memory. This complicates access to the memory during device tests. A test pattern program may
exceed the capacity of SQPG memory, and the time required to rewrite the test pattern could
have serious effects on production throughput.
For a GO/NO-GO test of this kind of embedded memory, an algorithmic pattern generator
(ALPG) option that generates a complicated test pattern can be added.
The ALPG easily generates test patterns, such as N2 and N3/2 patterns, that can improve the
defect detection rate, improving production throughput with one-path tests.
The ALPG also has an address descrambler function that generates physical addresses and a
cycle shift function that absorbs the latency caused by the pipeline structure.

3.2.10 AFM Option for Fail Analysis of Embedded Memory

The AFM (Address Fail Memory) option, which can be used when analyzing failure of embedded
memory, can be added. The memory test results for each cell can be captured into AFM and then
used for the bit map display and failure analysis.

3.2.11 SCPG Option for Scan Test

Many semiconductor manufacturers conduct scan tests to reduce test vector size without sacri-
ficing the defect detection rate.
The scan test requires a large scan pattern data, which may exceed SQPG memory capacity.
In T6573, T6563, and T6533, the scan pattern generator (SCPG) option can be installed for scan
tests. The SCPG option generates a scan pattern of up to 4 gigawords.

3.2.12 Analog Option for Analog Section Test

Recently, an increasing number of microprocessors contain an A/D converter or D/A converter.
In the T6573, T6563, and T6533, optional hardware can be added to test these converters.
The ADC and DCAP options are used to test A/D converters at high accuracy and high speed
for integral linear errors and differential linear errors.
The DAC option and DAW function are used to test the D/A converters at high precision and high
speed for integral linear errors and differential linear errors. For more information, refer to “T6500
SERIES ADDA OPTION PRODUCT DESCRIPTION (8409659).”

3.2.13 Iddq Option

The Iddq option is used to measure a very small current at high speeds when testing CMOS de-
vices that have a relatively high peak current in a short time in the dynamic operation and that
have very small current in static operations. For more information, refer to “IDDQ OPTION
PRODUCT DESCRIPTION (8370732).”

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

3.3 Performance Board Types

3.3 Performance Board Types

The T6573, T6563, and T6533 use HIFIX as the interface between the test head and performance
board.
Four types of HIFIX are available. Using one of the following HIFIX types allows the system to use
performance boards of other ADVANTEST test system models.

(1) 512pogoHIFIX
Used with the performance boards of the T3300 and T6600 AG heads.

(2) 512ZIFHIFX
Used with the 1024-channel performance boards of the T6600.

(3) 512AV2HIFIX
Used with the performance board of the T6600 AV2 HIFIX.

(4) 512SQHIFIX
Used with the performance board of the T6600 SQ HIFIX.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

4. RATE GENERATOR

4. RATE GENERATOR
The rate generator generates the master clock pulses used to define the test rate.
The test rate can be specified in a range from 8 ns (*) to 1 ms in a resolution of 31.25 ps.
A wide range of high-accuracy tests from an at-speed test to a stress test at a slow test rate can
be run.
The ability to change the test rate in real time using 32 timing sets makes it easy to test devices
such as MPUs at a different frequency in each cycle or modules that integrate cells that use differ-
ent frequencies.

*: The value varies depending on the system:

Table 4-1 Range of the Test Rate

System Range
T6573 8 ns to 1 ms
T6563 16 ns to 1 ms
T6533 32 ns to 1 ms

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5. SQPG THAT GENERATES LARGE-SIZE PATTERN DATA

5. SQPG THAT GENERATES LARGE-SIZE PATTERN DATA

5.1 Outline
The sequential pattern generator (SQPG) generates test patterns used for DUT function evalua-
tion.
The SQPG can generate patterns at up to 125 MHz in Normal mode or up to 250 MHz when the
pattern multiplex function is used. The standard size of pattern data that can be generated by the
SQPG is 16 megawords. This can be increased to up to 64 megawords.
The SQPG consists of vector generation control storage (VGCS) and a stimulus and expected vec-
tor (STE) buffer.
The STE buffer consists of a control table buffer (CTB) and a truth table buffer (TTB).
The VGCS contains instructions that control the pattern sequence.
The TTB contains pattern data of 3 bits per pin. The pattern data is used as applied patterns and
expected patterns for each cycle and for I/O switching control patterns.
The CTB contains signals that control the tester and PG for timing set decision or match detection.

VGCS

CTB TTB

DFM

C B A
Applied patterns/expected
patterns Fail information

FP

DUT

Figure 5-1 SQPG Block Diagram

Table 5-1 Pattern Capacity of SQPG

Unit Capacity Remarks

STE 16 M steps Standard
64 M steps Option
VGC 4 M steps Fixed

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5.2 DFM Used to Store Failure Information

5.2 DFM Used to Store Failure Information

The T6573, T6563, and T6533 use data fail memory (DFM) to store failure information used for
DUT failure analysis.
If a failure occurs during a functional test, failure information in the cycle is stored in the DFM. Fail-
ure information of up to 256 words per pin can be read into the DFM. The failure information in-
cludes the STE address, pattern count, timing set, and device output.
Data log and viewpoint tools and test plan programs can be used to read the failure information
stored in the DFM.

Table 5-2 DFM Capacity

Unit Capacity (words) Remarks

DFM 256 words Fixed

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5.3 Match Function

5.3 Match Function

5.3.1 Match Function
The match function detects a match between DUT output and an expected pattern to change the
pattern generation sequence. The function is used to initialize the DUT before starting a function-
al test or to test flash memory devices.

5.3.2 Match Types

The match function uses two types of mach detection method: a pulse train match and a pattern
match.

(1) Pulse train match

The pulse train match function detects a match when the expected values match the DUT
outputs in a given number of consecutive cycles. This function can detect matching from
up to 16 cycles for one DUT output pin.

(2) Pattern match

The pattern match function focuses on only one test cycle and detects a match when the
expected value matches the DUT output in the specific cycle. The function can detect
matching with multiple DUT output pins.

Pulse Train Match

/M /M ..... /M

DUT H L L H
/Pn

Matching can be detected from up to 16 cycles.

Pattern Match /M

H
/Pn

H
/Pn+1
DUT
L
/Pn+2

Matching can be detected from multiple pins in one cycle.

Figure 5-2 Match Types

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5.3 Match Function

5.3.3 Match Function Operation Modes

The pulse train match and pattern match can be executed in either of two operation modes: fixed
cycle match mode and fixed delay match mode.

(1) Fixed cycle match mode

A match can be detected at up to 125 MHz provided that dummy cycles are inserted after
a match is detected.

A
B
Match Pattern
C
D After a match is detected, 312 dummy cycles are
E inserted.

Dummy cycles

A B M M M M M M C D E

Start Stop
Cycle in which a match is detected

Figure 5-3 Fixed Cycle Match Mode

(2) Fixed delay match mode

A match can be detected without using dummy cycles provided that the test rate for match
detection cycles is restricted.

A
B
Match Pattern The test rate set for match detection must satisfy
C
D the following condition:
E Test rate ≥ strobe delay + 3.5 µs
F

Strobe 3.5µs

A B M M C D E F

Start Strobe
Cycle in which a match is detected

Figure 5-4 Fixed Delay Match Mode

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5.4 Register Loop Function

5.4 Register Loop Function

The register loop function repeats a test pattern program execution in an address part specified by
the test plan program.
Because a test pattern program needs to be executed repeatedly for a dynamic power current test,
another test pattern program is conventionally required in addition to the functional test pattern pro-
gram. The register loop function solves this problem because it permits the functional test pattern
program to be used as is for the dynamic power current test.
The function thus does not require an additional test pattern program for the dynamic power current
test, enabling a pattern memory to be used more efficiently.

NOP ! 0000
NOP ! 1111
NOP ! 1111 The register loop function repeats pattern execution in an address
part specified by the test plan program.
NOP ! 1111
Nop ! 0000

Figure 5-5 Register Loop Operation

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

5.5 Bump Function

5.5 Bump Function

The bump function transfers data stored in the output buffer memory (OBM) at a desired test pat-
tern address.
The following types of data can be stored in OBM for use in changing the test conditions during test
pattern program execution:
• Device power supply voltage
• Driver output voltage
• Comparator comparison voltage
• Load current
• Termination voltage or threshold voltage
• Wait time

The bump function makes it easy to perform a bump test of memory devices at high speeds.

5.5 V

4.5 V

OBM data transfer OBM data transfer

0V OBM data transfer

Device power-on
Pattern program start

Figure 5-6 Changing the Device Power Supply Voltage Using the Bump Function

5-6 Mar 9/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6. FRAME PROCESSOR (FP) FOR INPUT WAVEFORM GENERATION FOR DUTS AND OUTPUT

6. FRAME PROCESSOR (FP) FOR INPUT WAVEFORM GENERA-

TION FOR DUTS AND OUTPUT COMPARISONS

6.1 Outline
The frame processor generates input waveforms for the DUT and compares it with the data output
from the DUT independently for each pin (per-pin architecture).
The timing generator of the T6573, T6563, and T6533 resides in each frame processor. The timing
generator uses six timing edges independent for each pin, and uses up to 32 timing sets. With
these combinations, it is possible to generate complicated input waveforms for the DUT and to per-
form output comparisons.

Frame Processor

Frame Processor
Formatter

Rate Timing Pin

Generator Electronics DUT
Generator

Timing
SQPG Memory

Waveform
Memory

Digital
Compare

Figure 6-1 Block Diagram of Frame Processor (FP)

The frame processor consists of a timing generator, timing memory, waveform formatter, waveform
memory, and digital compare.
Timing set information is fed from the sequential pattern generator (SQPG) to the test generator
and frame processor.
The timing generator generates a timing edge for each timing set that is synchronized with the test
rate generated from the rate generator.
The waveform formatter generates a DUT input waveform based on the timing edge generated
from the timing generator and pattern data. With the voltage level specified by the pin electronics
driver, the waveform is applied to the DUT as an input signal.
The comparison of DUT output voltage levels is performed using the strobe signals generated from
the timing generator. The results of the comparison are compared with the expected pattern in the
frame processor to determine pass and fail results.

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.2 Timing Edge Functions

6.2 Timing Edge Functions

The timing generator of each frame processor generates six timing edges, TE1 to TE6.
As shown in Table 6-1, timing edges are categorized according to use: DUT input waveform gen-
eration, I/O control, and DUT output comparison.
Each timing edge is programmable to a desired value up to 4 x rate - 8 ns (up to 16 µs) at a reso-
lution of 31.25 ps. Each timing edge can be used to control output in each test cycle using the timing
set and pattern data.

Table 6-1 Standard Timing Edge Functions

Timing edge Function

TE1 DUT input waveform generation
TE2 DUT input waveform generation
TE3 DUT input waveform generation or I/O control
TE4 DUT input waveform generation or I/O control
TE5 DUT output comparison
TE6 DUT output comparison

RATE

Dr pin

TE1 TE2 TE3 TE4

Cp pin Dut-OUT Dut-OUT

TE5 TE6

Dut-OUT
I/O pin

TE1 TE2 TE5 TE3 TE4

or
TE6

Figure 6-2 Standard Uses of Timing Edges

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.3 DUT Output Comparison

6.3 DUT Output Comparison

Two timing edges, TE5 and TE6, are used to compare the DUT output voltage and comparison volt-
age.
These two timing edges are used as an edge strobe or window strobe.

VOH VOH

VOL VOL

Comparison point Comparison period

Strobe Strobe Strobe

Figure 6-3 Comparison with an Edge Strobe Figure 6-4 Comparison with a Window
Strobe
The edge strobe uses three comparison modes: normal mode, double-speed mode, and transition
mode.
Normal mode performs a comparison at one location in the cycle. Double-speed mode performs a
comparison at two locations. Transition mode detects DUT output transitions.

RATE
RATE

VOH VOH

VOL VOL

Figure 6-5 Output Comparison in Normal Mode Figure 6-6 Output Comparison in
Double-speed Mode

RATE RATE

VOH

VOL

Leading edge detection Trailing edge detection

Figure 6-7 Output Comparison in Transition Mode

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.3 DUT Output Comparison

Table 6-2 summarizes the DUT output states that can be detected in each comparison mode.

Table 6-2 Detectable DUT Output Status

Strobe type Comparison mode Detectable DUT output states

Normal Low, High, Hi-Z
Edge strobe Double-speed Low, High
Transition Low, High
Window strobe Normal Low, High, Hi-Z

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.4 Pattern Multiplex Function (PTMUX)

6.4 Pattern Multiplex Function (PTMUX)

The pattern multiplex function outputs two sets of pattern data during one test cycle.
The function generates a DUT input waveform and compares DUT output using timing edges TE1,
TE2, and TE5 in the first half of a test cycle and timing edges TE3, TE4, and TE6 in the second half
of the cycle.
The pattern multiplex function enables testing at a frequency (data rate) that is twice the basic fre-
quency.

Table 6-3 Timing Edge Functions When Pattern Multiplex Function is Used

Pattern Timing edge Function

TE1 DUT input waveform generation
First half TE2 DUT input waveform generation or I/O control
TE3 DUT output comparison
TE4 DUT input waveform generation
Second half TE5 DUT input waveform generation or I/O control
TE6 DUT output comparison

Test Rate
Data Rate
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

Dr(RZ waveform)

First half pattern data “1” “0” “1”

“1” “1” “0”
Second half pattern data

T1 T3 T1 T4 T5 T6

DUT-Out
I/O(NRZ waveform)

First half pattern data “1” “1” “L”

“0” “0” “H”
Second half pattern data

Figure 6-8 Timing Edge Functions When Pattern Multiplex Function is Used

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.4 Pattern Multiplex Function (PTMUX)

When the pattern multiplex function is used in combination with the pin multiplex function, measure-
ments can be executed at a frequency of four times the basic frequency (data rate).

Test Rate
Data Rate

Odd pin edge T1 T3 T3 T6

Even pin edge T1 T4 T5 T6

DUT-Out
Odd pin pattern
First half pattern “1” “X”

Second half pattern “0” “0”

Even pin pattern

First half pattern “1” “H”

Second half pattern “X” “L”

Figure 6-9 Example of Combined Use of Pattern Multiplex Function and Pin Multiplex Function

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

6.5 Multiple Clock Function (MCLK)

6.5 Multiple Clock Function (MCLK)

The multiple clock function generates up to four clock pulses within one test cycle.
A device test that uses more than one clock input for processing one data item requires extra pat-
tern data used to generate clock pulses.
For this kind of device test, the multiple clock function generates multiple clocks within one test cy-
cle by using a single pattern data item.
The multiple clock function enables the timing and the number of clocks to be set individually for
up to eight timing sets.

Test Rate

Slave Rate Slave Rate Slave Rate

Figure 6-10 Example of Multiple Clocks

6.6 Frequency Measurement Function

DUT output frequencies from 7.45 Hz to 200 MHz can be measured asynchronously to the timing
generator at all I/O pins. In frequency measurements, VOL of each I/O pin is used as the threshold
level. Doing so avoids output waveform noise that could result from an impedance mismatch on the
transmission line and permits frequency measurements at the optimum threshold level.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

7. PIN ELECTRONICS

7. PIN ELECTRONICS

7.1 Overview
The T6573, T6563, and T6533 pin electronics are designed to satisfy IEEE1394, LVDS, and CMOS
test requirements.
The driver voltage, comparison voltage, a load current value, clamp voltage, and a threshold level
can be set for each pin independently.
Since settings can be made flexibly, complicated test conditions are easy to set.

MDC
VIH UDC DC relay

Driver
Pin-out relay
50Ω ILL
VIL

Programmable load
VTT

I/O control

50Ω ILH

VOH

Comparator

VOL
DCLP
DCLM

Figure 7-1 Pin Electronics Configuration

7.2 Driver
The driver defines the voltages generated from the frame processor as VIH and VIL and outputs
them as the signal input to the device. A waveform with a transition time of 1.2 ns (20% - 80%, 0 -
3 V) and a minimum pulse width of 4 ns/3 Vp-p (2 ns/1 Vp-p) can be output.
The driver output amplitude can be set from 200 mVp-p to 8.0 Vp-p for LVS CMOS applications at
a resolution of 2 mV.

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

7.3 Comparator

7.3 Comparator
The comparator is a dual comparator consisting of two comparators for logical "H" comparison and
logical "L" comparison. Each comparator compares the DUT output at the strobe timing from the
frame processor.
The comparison voltage can be set from -2.0 V to 6.0 V at a resolution of 2 mV.

7.4 Programmable Load

The programmable load can be used to apply any load current to a device output pin. The program-
mable load eliminates the need to mount a current load circuit on the performance board.

7.5 Dynamic Clamp (DCLP)

The dynamic clamp is used to minimize the effects of refrected waves caused by an impedance
mismatch between the DUT and comparator.
An impedance mismatch on the transmission path between the DUT and comparator causes an
overshoot or undershoot in the comparator input section, with the result that the functional test re-
sults may not be determined correctly.
The dynamic clamp reduces this overshoot or undershoot to improve test accuracy.

VOH VOH

VOL VOL

Strobe Strobe
(test result: fail) (test result: pass)

DUT Output Waveform (without DCLP) DUT Output Waveform (with DCLP)

Figure 7-2 Using Dynamic Clamp

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

7.6 On-the-fly Terminator

7.6 On-the-fly Terminator

The device I/O pin may require I/O to be switched during a cycle, and the terminator must also be
turned on and off synchronously with I/O switching.
The on-the-fly terminator turns on when the driver is off and turns off when the driver is on. The on-
the-fly terminator makes the on/off switching in real time.

RATE RATE

VIH

Driver Driver Driver

VIL

T4(DRET) T3(DREL) T4(DRET) T3(DREL)

Driver
OFF ON OFF

Terminator ON OFF ON

Figure 7-3 On-the-fly Terminator Operation

7.7 Overvoltage Detection Circuit

The overvoltage detection circuit protects each pin.
When the overvoltage detection circuit detects that an overvoltage has been applied to pin elec-
tronics, the limit fail function is operated. The limit fail function opens the DC relay and pin-out relay
for all pins, causing the test result to be "failure".

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

7.8 Pin Multiplexing (PMUX)

7.8 Pin Multiplexing (PMUX)

The pin multiplex function combines two pins (an odd pin and an adjacent even pin) for use as one
pin, thereby generating two sets of pattern data within a single test cycle.
The timing edges and pattern data for two pins are used to apply input signals to the DUT and com-
pare and judge the DUT output to ensure the testing at a frequency (data rate) that is twice as high
as the basic frequency.
The pattern multiplex function (Chapter 6) is also used at the same time to ensure the testing at a
frequency (data rate) that is four times as high as the basic frequency.

RATE RATE

Odd pin Even pin Odd pin Even pin

pattern pattern pattern pattern
“1” “1” “L” “H”

Dut-OUT Dut-OUT

T1 T2 T1 T2 T6 T5

Timing edge Timing edge Timing edge Timing edge

of odd pin of even pin of odd pin of even pin

Figure 7-4 Operation when PMUX is Used

7-4 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

7.8 Pin Multiplexing (PMUX)

The following two methods are available for wiring on the performance board when pin multiplexing
is used.

Mode Device pin Wiring on the performance board

T66 mode Input pin Wiring to an odd (2n-1) pin
(Driver of the odd pin is used.)
Output pin Wiring to an even (2n) pin
(Comparator of the even pin is used.)
I/O pin Wiring to both odd (2n-1) and even (2n) pins
(Odd pin Dr and even pin Cp are used.)
T33 mode Input pin Wiring to an odd pin
Output pin (Odd pins Dr and Cp are used.)
I/O pin

Odd (2n - 1) pin Odd (2n - 1) pin

If device pin is an input pin

Figure 7-6 Wiring in T33 Mode
for PMUX

Even (2n) pin

If device pin is an output pin

Odd (2n - 1) pin

Even (2n) pin

If device pin is an I/O pin
Figure 7-5 Wiring in T66 Mode
for PMUX

If the device pin is an I/O pin, the I/O dead band exists in the T33 mode but it does not exist in the
T66 mode.

Sep 29/00 7-5

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

8. TWO DC PARAMETRIC TEST UNITS (MDC, UDC)

8. TWO DC PARAMETRIC TEST UNITS (MDC, UDC)

8.1 Outline
The multi-DC unit (MDC) and universal DC unit (UDC) are available for DC parametric tests. Both
units are capable of voltage source current measurements (VSIM), current source voltage mea-
surements (ISVM), and no current source voltage measurements (MVM).

8.2 Multi DC Unit (MDC)

The multi DC unit performs DC parametric tests at high speed.
Measurements can be performed by specifying and applying voltage ranging from -6 V to 8 V and
current ranging from +60 mA to -60 mA.
One MDC unit is provided for every 16 pins. The OS controls MDC units so that multiple pins are
measured simultaneously.

8.3 Universal DC Unit (UDC)

The universal DC unit is capable of application and measurement of a high voltage (±40 V) and
large current (±300 mA). The system has four UDC units, which can be connected to devices in the
following three ways:

(1) Using an UDC dedicated pin

(2) Assignment to a pin via MDC line

(3) Assignment to an analog option pin

Sep 29/00 8-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

8.3 Universal DC Unit (UDC)

Analog option pin

UDC1-dedicated pin
UDC2-dedicated pin
UDC3-dedicated pin
UDC4-dedicated pin
UDC1 MDC1 P1
P2
:
UDC2 P16
MDC2 P17
P18
UDC3 :
P32
UDC4
MDC8 P113
P114
:
P128

MDC25 P385
P386
:
P400
MDC26 P401
P402
:
P416

MDC32 P497
P498
:
P512

Figure 8-1 DC Parametric Test Unit Controller

8-2 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

8.3 Universal DC Unit (UDC)

Table 8-1 Correspondence between DC Parametric Test Units and Pins

UDC No. MDC (connect to) I/O pin Analog option pin
MDC1 P1 to P16
MDC2 P17 to P32
AWG1
MDC3 P33 to P48 DGT1
MDC4 P49 to P64 VRH1
UDC1 VRL1
MDC5 P65 to P80
VOFFSET1
MDC6 P81 to P96
MTXn*1
MDC7 P97 to P112
MDC8 P113 to P128
MDC9 P129 to P144
MDC10 P145 to P160
AWG2
MDC11 P161 to P176 DGT2
MDC12 P177 to P192 VRH2
UDC2 VRL2
MDC13 P193 to P208
VOFFSET2
MDC14 P209 to P224
MTXn*1
MDC15 P225 to P240
MDC16 P241 to P256
MDC17 P257 to P272
MDC18 P273 to P288
AWG3
MDC19 P289 to P304 DGT3
MDC20 P305 to P320 VRH3
UDC3 VRL3
MDC21 P321 to P336
VOFFSET3
MDC22 P337 to P352
MTXn*1
MDC23 P353 to P368
MDC24 P369 to P384
MDC25 P385 to P400
MDC26 P401 to P416
AWG4
MDC27 P417 to P432 DGT4
MDC28 P433 to P448 VRH4
UDC4 VRL4
MDC29 P449 to P464
VOFFSET4
MDC30 P465 to P480
MTXn*1
MDC31 P481 to P496
MDC32 P497 to P512

*1: The same UDC as HLFGnP, HLFDnP, HLFDnNn connected to MTXn is assigned to
the MTX pin.

Sep 29/00 8-3

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

9. DEVICE POWER SUPPLY

9. DEVICE POWER SUPPLY

9.1 Overview
The T6573, T6563, and T6533 have eight standard device power supplies (DPSs), which have ex-
cellent variable load characteristics. The number of DPSs can be expanded up to 32 in units of 8.
One DPS can supply voltages up to 8 V and currents up to 2 A. For a device that requires more
than 2 A to be supplied, multiple DPSs can be connected in parallel to the device.
The connection, the number of channels, and current capacity of a DPS vary depending on the type
of HIFIX used.

(1) 512pogoHIFIX

DPS channel
PS pin
(on the performance board)
1
9 1
17
1
10 2
18

7
15 7
23
8
16 8
24

25 25

31 31
32 32

Figure 9-1 DPS Connection when 512pogoHIFIX is Used

When 512pogoHIFIX is used, channels DPS1 to DPS24 are connected in parallel in three-
channel units and then are connected to PS1 to PS8 on the performance board. DPS25 to
DPS32 are connected to PS25 to PS32. The current capacity of PS1 to PS8 is 6 A (2 A x
3), and that of PS25 to PS32 each is 1 A.

Sep 29/00 9-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

9.1 Overview

(2) 512ZIFHIFIX and 512SQHIFIX

DP pin
DPS channel
(on the performance board)

1 1

2 2

3 3

30 30
31 31
32 32

Figure 9-2 DPS Connection when 512ZIFHIFIX is Used

When 512ZIFHIFIX and 512SQHIFIX are used, DPS1 to DPS32 are connected to DP1 to
DP32 on the performance board.
The current capacity of DP1 to DP32 each is 2 A.
DP1 to DP32 can be connected in parallel as desired on the performance board.

(3) 512AV2HIFIX

PS pin
DPS channel
(on the performance board)

1 1

2 2

3 3

8 8

9 25

15 31
16 32

Figure 9-3 DPS Connection when 512AV2HIFIX is Used

When 512AV2HIFIX is used, DPS1 to DPS16 are connected to PS1 to PS8 and PS25 to
PS32 on the performance board.
The current capacity of PS1 to PS8 and PS25 to PS32 each is 2A.
PS1 to PS8 and PS25 to PS32 can be connected in parallel as desired on the performance
board.

9-2 Nov 8/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

9.2 Current Measurement Function

9.2 Current Measurement Function

Each DPS has a current measurement function. The function has seven current measurement
ranges between 8 µA and 2 A to enable measurement of power currents from when the device is
in dynamic operation status to when it is in static operation status.
For the measurement range of very small currents, the DPS can supply currents down to 500 mA.
Therefore, even for measurement of power current in the static status, the measurement range
need not be changed for DUT operation and measurement of very small currents.

9.3 Voltage Source Voltage Measurement Function

The DPS has a voltage source voltage measure function (VSVM) for the power supply pin contact
test. In addition to the contact test, the function can also check for disconnection between the DPS
force line and sense line on the performance board.

9.4 Parallel Operation Function

To test a device requiring a power current of 2 A or higher, multiple device power supplies can be
connected on the performance board for parallel operation. All device power supplies can also be
connected and operated in parallel if necessary.
Dynamic power current measured during parallel operation is obtained as the sum of all channels
connected in parallel. Very small power current is measured by only the DPS assigned the smallest
channel number. Any DPS not used for measurement is disconnected when the measurement be-
gins and reconnected after the measurement ends.

9.5 Average Current Measurement Function

The average current measurement function measures the average, minimum, and maximum pow-
er currents at the pattern addresses and at the time specified by the timer.
The function can measure the average current at a sampling period of 100 µs for up to 13 s using
the sample & hold circuit and digital adder.

Sep 29/00 9-3

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

9.6 Programmable Slew Rate

9.6 Programmable Slew Rate

The rise and fall times for the DPS (power supply slew rate) can be set as desired. The rise and fall
times per volt can be adjusted from 25 µs to 25 ms in 6.25 µs steps.
Programmable slew rate enables execution of the tests, which are suitable for the actual use status
of the device:

1V
V = 64 mV

0V

Slew rate

Figure 9-4 Control of Slew Rate

9.7 Alarm Functions

The DPS has the following alarm functions:
• Current clamp detection alarm
When the current reaches the clamp value, an alarm is generated.
• Abnormal Kelvin voltage detection alarm
When a voltage drop between the device end and DPS exceeds the specified value, an alarm
is generated.
• Abnormal guard current detection alarm
When a guard pin contacts the ground or other pins and an abnormal current occurs, an alarm
is generated.
• Abnormal oscillation detection alarm
When the DPS oscillates, an alarm is generated.

9-4 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

10. DUT INTERFACE

10. DUT INTERFACE

10.1 Test Head

The following signals and power supplies are available for the T6573, T6563, and T6533 test heads
as DUT interfaces.
The signals and power supply are connected to the device via the HIFIX and performance board.

Table 10-1 Signals and Power Supply on Test Head

Signal and power supply name Use

I/O pin Used for driver output and comparator input during DC
test and functional test.
LOAD Used to control the connection of the DUT to the load cir-
cuit. This signal is provided for each I/O pin.
CW I/O port for control word input/output. Used to control an
additional circuit on the performance board.
DPS Used as power supply for the device.
UDC Used for a DC test.
Utility power supply General-purpose power supply with a fixed voltage value.
+15 V Used to supply power to the additional circuit on the per-
-15 V formance board.
PBVCC
PBVEE
RLVCC
PCON(CPS) Used to control the bypass capacitor relay.
LCON(CLD) Used to control connection of the load circuit.
HLFG Used for ADC measurement section output.
HLFD Used for DAC measurement section input.
VRH/VRL Used for reference supply output.
MTX Relay matrix that can be used at the user’s option. Used
to distribute the analog I/O pin to multiple device pins.

Sep 29/00 10-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

10.2 HIFIX and Performance Board

10.2 HIFIX and Performance Board

The interface between the test head and the performance board (PB) is called HIFIX. Four types
of HIFIX are available for the T6573, T6563, and T6533.
Each type HIFIX uses a different type of performance board.

Table 10-2 Performance Board and HIFIX

Type number of general-purpose PB

HIFIX type Remarks
Manual Wafer
512pogoHIFIX T100661 T100662 In common with T6600 512-channel PB*
T11144 T11149 In common with PB for T3300 AG head *
512ZIFHIFIX T100564 T100563 In common with T6600 1024-channel PB*
512AV2HIFIX T101383 T101761 In common with T6600 PB for AV2HIFIX
option *
512SQHIFIX T102151 T102176 In common with T6600 PB for SQHIFIX
option *
*: If the T6573, T6563, and T6533 are equipped with the Common Unit, the same performance
board can be used.

Figure 10-1 Connecting the HIFIX and the Performance Board

10-2 Nov 8/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

10.3 HIFIX Resources

10.3 HIFIX Resources

The resources vary according to the HIFIX that is used.

Table 10-3 Available Resources for Each Type of HIFIX

512ZIFHIFIX
Type 512pogoHIFIX 512AV2HIFIX
512SQHIFIX
I/O pin 512 512 512
LOAD 512 512 256
CW 64 64 64
Device power supply (DPS) 16* 32 16
UDC 4 4 4
PCON(CPS) 16 32 16
LCON(CLD) 3 3 3
HLFG 4 4 4
HLFD 4 4 4
VRH/VRL 4/4 4/4 4/2
MTX 16 16 16

*: DPS1 to DPS24 are connected in the HIFIX in three channel units in parallel: 8 channels +
DPS25 to DPS32 are connected individually: 8 channels.

The wire length and I/O tpd of performance board are shown below.

Table 10-4 Specified Wiring Length and I/O tpd for Each Performance Board

512pogoHIFIX
512ZIFHIFIX 512SQHIFIX Remarks
512AV2HIFIX
Specified wiring 1.0 ns 1.0 ns 1.0 ns
length
I/O tpd 3.7 ns 3.6 ns 4.6 ns Each I/O tpd includes the wiring
length on the performance board.

Nov 8/02 10-3

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

11. OPTION PG

11. OPTION PG

11.1 ALPG (OPTION): GENERATING COMPLEX MEMORY PATTERNS

11.1.1 Overview
The Algorithmic Pattern Generator (ALPG) generates memory test patterns.
Since a huge test pattern program file may be required depending on the memory size or test
algorithm, generating a memory test pattern with the SQPG can increase test time for such rea-
sons as the need to retransfer the pattern program.
If an address generation algorithm is programmed, however, the ALPG can be used to efficiently
generate a huge number of test patterns using fewer program steps.
As a result, test pattern transfer time and space requirements for SQPG are minimized, improv-
ing throughput.
The ALPG consists of a Writable Control Store (WCS), an address generator, a data generator,
and a control signal generator.
The WCS stores instructions used for address and data generation.
The address generator generates an address pattern in response to an address operation in-
struction.
The data generator generates a memory write pattern and comparison pattern.
The control signal generator generates the signals required to control the memory.
Pattern generation by the ALPG is controlled by the SQPG.
The ALPG only generates addresses, data, and control signal patterns. The pattern sequence is
controlled by the SQPG.
A logical OR operation is performed on pattern data generated by the ALPG and the TTB data
of the I/O pin, and the result is supplied to the FP.

ALPG SQPG

WCS
Control

Control signal Address

Data generator
generator generator

PDS

FP

DUT

Figure 11-1 Pattern Generation by the ALPG

Sep 27/01 11-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

11.1 ALPG (OPTION): GENERATING COMPLEX MEMORY PATTERNS

Table 11-1 shows the ALPG specifications.

Table 11-1 ALPG Specifications

Maximum operating frequency 125 MHz
WCS 1 kwords
Address generation X0 to X15
Y0 to Y15
Data generation DA0 to DA17, DB0 to DB17
Control signal R, W, M1 to M2, C0 to C15

11.1.2 Connection to any I/O Pin from the PDS

The PDS assigns the pattern data generated by the ALPG to an I/O pin.
The PDS output data is ORed with the TTB data of the I/O pin and then supplied to the frame
processor.

11.1.3 Address Descramble Function

The address descramble function associates the logical addresses generated by the ALPG with
physical memory cells.
Programming the disturb test for cells is difficult, since the layout of the physical cells does not
directly correspond to the logical addresses.
Because the address descramble function matches the physical cells with logical addresses, it
makes it much easier to perform a disturbance test.

11.1.4 Auto Refresh Function

The auto refresh function generates a refresh pattern at fixed intervals while the ALPG is gener-
ating patterns.
In a DRAM, the potential (data) stored in the memory cell capacitor leaks with the passage of
time. The potential must therefore be maintained by rewriting (refreshing) each memory cell at
fixed intervals.
The auto refresh function is used to perform this operation automatically.
When the refresh pattern has been executed, the auto refresh function returns to the pattern cy-
cle after the cycle where the interrupt occurred.
The auto refresh function can also be used to execute a refresh test for evaluating the ability of
a device to retain data.

11-2 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

11.1 ALPG (OPTION): GENERATING COMPLEX MEMORY PATTERNS

11.1.5 Cycle Shift Function

The cycle shift function delays pattern generation by the ALPG for an arbitrary number of cycles.
Because recent devices contain high-speed memory, data output may delay by some cycles
from the corresponding data input or control signal input.
The cycle shift function can delay ALPG pattern generation for up to 7 cycles, allowing such de-
vices to be tested.
When the cycle shift function is used, data can be tested and evaluated without any restrictions
on the setting range of the strobe edge.
Cycle delays can also be used for input patterns and I/O control signals in addition to an expected
pattern.

11.1.6 Regional Inversion Function (ARIRAM)

The regional inversion function inverts the data at a specific address. For DRAM, since data that
is the reverse of the input/output data is often written to specific addresses, such data must be
inverted for a test that uses regular patterns, such as checker board and stripe patterns.
Although creating a pattern program that inverts data at a specific address can solve this prob-
lem, creation of such a program may become difficult if the area to be inverted is complicated.
The regional inversion function can be used to perform this kind of test. The function easily in-
verts data in a specific area without the need to create complicated pattern programs.

11.1.7 Address Fail Memory AFM (Option)

Address Fail Memory captures the test result for each cell during the memory test.
The test results are used to display the fail bit map and analyze the failure.

Table 11-2 AFM Specifications

Item Specification

Maximum operating frequency 125 MHz

Memory configuration Maximum size 36 Mbit/28 pin
Bit configuration ×1, ×4, ×9, ×18, ×36
Operation Failure Store
Parallel test configuration Bit configuration ×1 ×4 ×9 ×18 ×36
Number of 512 pin/DUT
pins per
256 pin/DUT 32 MW 8 MW 4 MW 2 MW 1 MW
DUT
128 pin/DUT
64 pin/DUT 16 MW 4 MW 2 MW 1 MW -

Oct 4/02 11-3

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

11.2 SCPG (OPTION) FOR GENERATING SCAN PATTERNS

11.2 SCPG (OPTION) FOR GENERATING SCAN PATTERNS

11.2.1 Overview
The scan pattern generator (SCPG) generates a large number of scan patterns when a device
which is designed by scan path method such as LSSD or boundary scan is tested (scan test).
A scan test requires a large pattern program that exceeds the SQPC capacity.
However, only the pattern for the scan pin changes, but the patterns other than it do not change.
The SCPG option is provided for testing this type of device.
In a scan test that uses the SCPG, the initialization pattern generated by the SQPG is used to
place the device in the scan test state. Scan patterns generated from the SCPG are then contin-
uously applied to the device.
This method ensures high-speed testing without the need to rewrite the PG when a pattern pro-
gram exceeding the SQPG capacity is required.

Initialization pattern
SQPG
Primary pattern

Scan pattern

SCPG

Primary pattern SQPG

Scan pattern
SCPG

SQPG

Figure 11-2 Scan Test Pattern Generation

Only the pattern for the scan pin is stored in the SCPG. Generation of the pattern stored in the
SCPG is controlled from the SQPG, and the pattern is used as the pattern input for the scan pin
and the expected pattern for the scan pin.

SCPG SQPG

Control

PDS

FP

DUT

Figure 11-3 Concept of SCPG Output

11-4 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

11.2 SCPG (OPTION) FOR GENERATING SCAN PATTERNS

The 4Gigabits or 16Gigabits SCPG pattern memory can be selected.

The pattern memory can generate a scan pattern of up to 1 or 4 Gigawords.
Four to 64 scan pins can be supported.

Scan pattern address depth Number of scan Maximum operating

4GB option 16GB option pins frequency

1Gigawords 4Gigawords 4
512Megawords 2Gigawords 8
125 MHz
256Megawords 1Gigawords 16
128Megawords 512Megawords 9, 18, 32
64Megawords 256Megawords 48, 64 62.5 MHz

The SCPG is used to generate a digital pattern (DAW) for D/A converter testing.

11.2.2 Pattern Data Assignment to a Pin by the Programmable Data Selector

(PDS)
The Programmable Data Selector(PDS) assigns the pattern data generated by the SCPG to an
I/O pin.
The PDS output data is ORed with the TTB data of the I/O pin and then supplied to the frame
processor.

Sep 27/01 11-5

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

12. A/D AND D/A CONVERTER MEASUREMENT OPTION

12. A/D AND D/A CONVERTER MEASUREMENT OPTION

This option is used for DC parametric measurement (such as a differential linearity, integral linear-
ity, and offset) for analog circuitry at high speeds. This enables a maximum of 4 devices in a parallel
test (4 channels). This option provides the following functions:

(1) Analog waveform generation function for A/D converter measurement (HLFG function for
converters).

(2) Output data capture for A/D converter (DCAP function).

(3) Data generator for D/A converter (SCPG DAW function).

(4) Analog waveform capture for D/A converter (HLFD function for Converter).

(5) Sampling clock controller (LSYNC function)

(6) Analog reference supply (VREF function)

(7) MTX function (MTX function)

12.1 Analog Waveform Generation Function for A/D Converter Measurement

(HLFG function for converters)
The HLFG function is provided for a maximum of four channel A/D converter measurement. This
function enables switching between the LF mode (Low Frequency Mode) and the HF mode (High
Frequency Mode). Therefore, this enables device tests that require analog input signals from DC
tests to high-speed tests.

12.2 Output Data Capture for A/D Converter (DCAP function)

This DCAP function enables to capture 32 bit data from any I/O pins using FMUX. The data capture
is performed in accordance with the pattern control. The various pieces of data such as the serial
format or the parallel format are converted by the hardware at high speeds.

12.3 Data Generator for D/A Converter (SCPG DAW function)

This function enables to generate the digital data from the digital pins for the D/A converter evalu-
ation using the DAW function of the SCPG board. This enables switching of the digital waveform
data to any of 64 waveforms in real-time. This is also applicable to the LOOP function (24 bit).

12.4 Analog Waveform Capture for D/A Converter (HLFD Function for Converter)
The HLFD function is used to capture analog waveforms from a maximum of four channel D/A con-
verters. This function enables switching between the LF mode (Low Frequency Mode) and the HF
mode (High Frequency Mode). Therefore, this enables capturing of analog signals for DC tests to
high-speed tests.

Sep 27/01 12-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

12.5 Sampling Clock Controller (LSYNC function)

12.5 Sampling Clock Controller (LSYNC function)

The four channel clocks are provided for the analog options. The clock generator is controlled by
patterns.

12.6 Analog Reference Supply (VREF function)

The eight channel power supply units are provided for analog circuitry.

12.7 MTX function

16 channel MTX is available. This function enables to execute the analog multi-channel device test
without using additional relays on the performance board.

12-2 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

13. MULTIPLE DEVICE PARALLEL TEST FUNCTION

13. MULTIPLE DEVICE PARALLEL TEST FUNCTION

To improve throughput, the T6573, T6563, and T6533 can test multiple devices in parallel. The par-
allel test function can be used for DC parametric tests, functional tests, AC parametric tests, fre-
quency measurements, and A/D and D/A converter tests.
A 256-pin system can test up to four devices in parallel, and a 512-pin system can test up to eight
devices in parallel.
In an A/D or D/A converter test, up to four devices can be tested simultaneously.
I/O pins can be assigned to one DUT in one of 64 pins, 128 pins, and 256 pins units.
For parallel test of multiple devices, tester resources are assigned to each DUT, as shown below.

Table 13-1 Tester Resource Assignments when 64 Pins are Assigned to Each DUT
(512-pin System)
Number of DPS channels HLFG/
MDC UDC VRH/VRL
Maximum
HLFD
I/O pin No. channel channel Standard channel
configuration channel
No. No. configuration No.
(*1) No.
DUT1 1 to 64 1 to 4 1 4
1
DUT2 65 to 128 5 to 8 1 4
DUT3 129 to 192 9 to 12 1 4
2
DUT4 193 to 256 13 to 16 1 4 Select 1 to Select 1 to
DUT5 257 to 320 17 to 20 1 4 4. (*2) 4. (*2)
3
DUT6 321 to 384 21 to 24 1 4
DUT7 385 to 448 25 to 28 1 4
4
DUT8 449 to 512 29 to 32 1 4

Table 13-2 Tester Resource Assignments when 128 Pins are Assigned to Each DUT
(512-pin System)
Number of DPS channels HLFG/
MDC UDC VRH/VRL
Maximum
HLFD
I/O pin No. channel channel Standard channel
configuration channel
No. No. configuration No.
(*1) No.
DUT1 1 to 128 1 to 8 1 2 8 1 1
DUT2 129 to 256 9 to 16 2 2 8 2 2
DUT3 257 to 384 17 to 24 3 2 8 3 3
DUT4 385 to 512 25 to 32 4 2 8 4 4

*1 The number of channels that can be connected to a DUT and the current capacity vary de-
pending on the HIFIX used. For more information, refer to Chapter 9, "DEVICE POWER SUP-
PLY."
*2 The OS does not assign or control channels.
The program must select and control target channels.

Sep 29/00 13-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

13. MULTIPLE DEVICE PARALLEL TEST FUNCTION

Table 13-3 Tester Resource Assignments when 256 Pins are Assigned to Each DUT
(512-pin System)
Number of DPS channels HLFG/
MDC UDC VRH/VRL
Maximum
HLFD
I/O pin No. channel channel Standard channel
configuration channel
No. No. configuration No.
(*1) No.
DUT1 1 to 256 1 to 16 1 to 2 4 16 1, 3 1, 3
DUT2 257 to 512 17 to 32 3 to 4 4 16 2, 4 2, 4

Table 13-4 Tester Resource Assignments when 64 Pins are Assigned to Each DUT
(256-pin System)
Number of DPS channels HLFG/
MDC UDC VRH/VRL
Maximum
HLFD
I/O pin No. channel channel Standard channel
configuration channel
No. No. configuration No.
(*1) No.
DUT1 1 to 64 1 to 4 2 8 1 1
1
DUT2 65 to 128 5 to 8 2 8 2 2
DUT3 129 to 192 9 to 12 2 8 3 3
2
DUT4 193 to 256 13 to 16 2 8 4 4

Table 13-5 Tester Resource Assignments when 128 Pins are Assigned to Each DUT
(256-pin System)
Number of DPS channels HLFG/
MDC UDC VRH/VRL
Maximum
HLFD
I/O pin No. channel channel Standard channel
configuration channel
No. No. configuration No.
(*1) No.
DUT1 1 to 128 1 to 8 1 4 16 1, 3 1, 3
DUT2 129 to 256 9 to 16 2 4 16 2, 4 2, 4

*1 The number of channels that can be connected to a DUT and the current capacity vary depend-
ing on the HIFIX used. For more information, refer to Chapter 9, "DEVICE POWER SUPPLY."

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

14. HRS FOR HIGH-SPEED PATTERN TRANSFER (OPTION)

14. HRS FOR HIGH-SPEED PATTERN TRANSFER (OPTION)

The larger a test pattern program, the more time is required to transfer the pattern program file to
the pattern generator. Because a test cannot be performed while the pattern program file is trans-
ferred, the increased transfer time adversely affects productivity.
The high-speed reload server (HRS) is a pattern file-specific server that transfers pattern program
files through a dedicated line of 40 megabytes per second. The HRS can be connected to up to
eight test systems.
The HRS shortens the pattern program file transfer time and improves productivity.
The HRS can also load the pattern program file for the next test from another computer while it is
not transfering pattern program file to the pattern generator. This operation has no adverse effects
on test system operation.
The standard HRS has a 72-gigabyte save area for pattern program files. The size of the save area
can be expanded up to 504 gigabytes in 72-gigabyte increments.

Host computer

Up to 8 test systems

TC TC

HRS
PG PG
Up to 504 GB

Test System Test system

Up to 40 MB/Sec

Figure 14-1 Pattern Transfer by HRS

Sep 29/00 14-1

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

15. COMPUTING ARCHITECTURE

15. COMPUTING ARCHITECTURE

15.1 Overview
The T6573, T6563, and T6533 use either the TC4 or TC7 in the computing architecture.

(1) TC4
The T6573, T6563, and T6533 use the TC4 dual-SPARC processor computing architec-
ture to achieve high throughput (Figure 15-1).
One processor, on which VxWorks runs, is used as the Real Time (RT) processor that con-
trols the tester. Another processor is used as the Non Real Time (NRT) processor that con-
trols the entire test system and processes the test results.
Solaris runs on the NRT processor equipped with a graphical user interface that is used to
run test system file management software and other tools.
The NRT processor can be connected to a network.
The RT processor controls the testing functions only. It achieves maximum throughput dur-
ing device testing and a high level of repeatability for the evaluation of device characteris-
tics.

Network

Network I/F (10Base or 100Base)

NRT processor (Engine) RS232

SPARC CPU
OS: Solaris

VME-Bus
Peripheral
RT processor device
(Tester controller)
SPARC CPU
OS: VxWorks GPIB

Handler
Tester Bus
or
prober
Tester
hardware

Figure 15-1 TC4 Computing Architecture

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

15.1 Overview

Table 15-1 TC4 Configuration

NRT processor RT processor

(Engine) (Tester controller)
CPU Ultra SPARC 300 MHz Ultra SPARC 300 MHz
Memory 256 Mbyte 256 Mbyte
OS Solaris VxWorks
18 Gbyte Hard Disk drive GPIB interface
(One optional drive can be added)
CD-ROM drive
Floppy disk drive
Peripheral device Monitor
15-inch LCD built into the processor unit
or
22-inch external CRT
Keyboard/mouse
Network I/F 10Base or 100Base

(2) TC7
The T6575, T6565, and T6535 computing system use the UNIX operating system, and
dual-SPARC processors to ensure high-speed operation. An open architecture has been
implemented using this platform, integrating the test system, transporting test data, and
simplifying the use of third-party software.
The dual-SPARC processor configuration has one of the processors assigned to task man-
agement exclusively, which has made it possible to reduce the time needed for testing de-
vices, achieve very reliable and easily reproducible device characteristic evaluations
reliability and reproducibility, and maximize testing throughput. Figure 15-2 shows the ba-
sic components of the T6672 test system.

15-2 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

15.1 Overview

Ethernet

Dual-processor
(SPARC CPU)
(OS: Solaris)

Tester bus
GPIB
Tester bus I/F

Tester hardware

Figure 15-2 TC7 Computing System Architecture

Table 15-2 TC7 Configuration

Specification
CPU Ultra SPARC IIIi 1.28 GHZ × 2CPU
Memory 2 Gbyte
OS Solaris
36 Gbyte Hard Disk drive
(One optional drive can be added)
CD-ROM drive
Floppy disk drive
Monitor
Peripheral device
15-inch LCD built into the processor unit
or
22-inch external CRT
Keyboard/mouse
GPIB interface
Network I/F 10Base-T, 100Base-T, 1000Base-T

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

16. OPERATING ENVIRONMENT

16. OPERATING ENVIRONMENT

16.1 Using the NRT Processor

The NRT processor is used to operate T6573, T6563, and T6533.
The NRT processor uses the UNIX operating system (Solaris).
The display and keyboard used to perform operations can be either built in or supplied separately.
When the display is built into the mainframe, it requires no extra floor space.
The external type is a 22-inch large display that provides a larger area for evaluation and debug-
ging.

The following functions can be performed using the NRT processor:

• Editing the test program and pattern program
• Compiling pattern programs
• Starting and stopping the test controller
• Loading test programs
• Setting test conditions
• Executing and controlling tests
• Evaluating the device
• Debugging test programs
• Executing the system diagnostic program
• Executing the calibration program and initialization program

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

16.2 Using the Control Panel

16.2 Using the Control Panel

The control panel is a portable terminal, which includes the functions listed below. It can be placed
anywhere allowing easy operation of the tester.
• Starting and stopping tests
• Accessing function keys
• Controlling alarm
• Displaying test results
• Displaying Production or Standard mode
• Displaying the hardware (CAL and INIT) status
• Displaying the test plan name and test ID
• Displaying the category and standard counter value
The control panel makes it easier for the operator to perform test operations on the production line.
It also supports tester operations during device evaluation.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

16.3 Batch Operation (Option) Using TIM Software

16.3 Batch Operation (Option) Using TIM Software

The test integration manager (TIM) is software that enables batch operations for test systems and
probers, improving operability on mass production lines.
The usual method of changing the device type on a mass production line requires individual oper-
ations on both the prober and test system. The TIM implements the following operating environ-
ments:
• Batch setup from a PC
• Batch setup from the prober
• Centralized control of the test program and test results

(1) Batch setup from a PC

A PC connected to a network can be used to perform the following operations:
• Batch setup of the test system and prober
• Monitoring the test system status
• Monitoring the prober status
• Displaying the wafer map data obtained by the prober

Host computer

Device test program

Test results Device type

Monitor

PC
Test system Prober

Control information

Figure 16-1 Batch Operations from a PC

Batch processing allows operations to be performed from a location away from the mass
production line and test results to be monitored.
(The methods of setting prober and monitoring status vary depending on the prober man-
ufacturer.)

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

16.3 Batch Operation (Option) Using TIM Software

(2) Batch setup from the prober

Entering test device type information from a barcode reader connected to the prober en-
ables the test system and prober to be set up in a batch processing.
Test results and test system status (initialization or runtime errors) can also be displayed
on the prober operation panel.

Host computer

Device test program

Test result

Monitor

Device type

Barcode reader

Test system Prober

Figure 16-2 Batch Operation from the Prober

(3) Centralized control of the test program and test results

The host computer can be used to control the test program and test results. Simply input-
ting test device information automates the following operations:
• Downloading a test program for the device under test
• Uploading test results

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17. Viewpoint SOFTWARE

17. Viewpoint SOFTWARE

17.1 Overview
The system software Viewpoint which has been used in the T6600 series, is used on the T6573,
T6563, T6533 and it can provide following test environment.
• Debugging the device test program
• Testing the device
• Evaluating and analyzing device characteristics
Viewpoint uses a test controller via a GUI and a comprehensive tools to provide powerful develop-
ment and mass production line operating environments.

User

Test execution
Debugging
Characteristic evaluation/analysis

Viewpoint
(Operating system)

Tools
TDL interpreter
Compiler
Tester library

Solaris VxWorks

Tester
hardware

Figure 17-1 Viewpoint Software

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T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.2 Viewpoint Programming Language and Test Execution Environments

17.2 Viewpoint Programming Language and Test Execution Environments

Device test programs used with Viewpoint are written in an object-oriented programming language
called Test Description Language (TDL).
The user can efficiently create highly reusable test programs using classes provided by the system.
The test execution environments include an online environment in which the test system is actually
used and an offline environment in which a tester simulator (Vsim) is used. The same program will
run in both environments.

Test program
User-created
User-defined
class/function

Compiler/TDL interpreter

Viewpoint

Tester library
Vsim

Tester emulator

Figure 17-2 Test Program Execution Environment

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3 Tools
Viewpoint has comprehensive tools for efficiently creating and debugging test programs and eval-
uating and analyzing a device.
The tools are linked to one another, so other tools can be called from the evaluation tool.
Using the tools reduces the Turn Around Time (TAT) for device evaluation and analysis.

17.3.1 Siteseer
Siteseer is a test generation tool that allows you to create test plan programs without requiring
any special knowledge of test program languages. Using GUI-based tools such as Flow Editor,
Test Editor, Pinmap Editor, or Timing Chart Editor, you can create and modify test programs eas-
ily.

Figure 17-3 Siteseer

Sep 29/00 17-3

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.2 Viewpoint Console

Viewpoint Console is the main control and monitor window for Viewpoint applications. This Tool
is used to control the execution of test programs, set debug modes, display test results, set data
logs, access other tools, enter command line instructions, and display system messages.

Figure 17-4 Viewpoint Console

17-4 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.3 SystemViewer
SystemViewer is a tool that allows you to display or modify test conditions.

Figure 17-5 SystemViewer

Sep 29/00 17-5

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.4 Pattern Viewer

Pattern viewer is a tool that allows you to display or modify test patterns and monitor pattern pro-
gram execution status.
Since it can display the location of failures, it is useful for debugging test patterns.
Linking to the Logic Analyzer or Oscilloscope tool allows you to check waveforms using the Pat-
tern Viewer.

Figure 17-6 Pattern Viewer

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.5 Logic Analyzer Tool

The Logic Analyzer tool (LA Tool) can monitor waveforms in a logic analyzer-like image and can
modify timing conditions. It is useful for finding failure locations in a device and helps you to an-
alyze the cause of individual failures.
Linking to the Oscilloscope tool allows you to monitor waveforms at a high-resolution using the
Logic Analyzer tool.

Figure 17-7 Logic Analyzer Tool

Sep 29/00 17-7

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.6 Oscilloscope Tool

The Oscilloscope tool (OSC Tool) is used to display device output waveforms as an oscilloscope
image after sampling the waveforms with high resolution. This tool made it possible to save fail-
ure analysis results or displayed waveforms to a file.

Figure 17-8 Oscilloscope Tool

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.7 Shmoo2
This tool allows you to display shmoo plots whether they are 1 to 2.5 dimensions. This tool has
the ability to display fail addresses, stack shmoo plots, and link to the LA tool. Furthermore, the
condition data on any grid of this tool can be referenced to or modified by System Viewer, or this
tool can be linked to the Mask tool in order to display specific pattern addresses.

Figure 17-9 Shmoo2

Sep 29/00 17-9

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.8 DataScan
DataScan repeats a test while increasing or decreasing the values of parameters in focus and
displays the test result.

Figure 17-10 DataScan Window Layout

17-10 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.9 Margin
This tool is used to measure the operational tolerance of the DUT. This helps to find the tolerance
of the device when it passes, and examine the cause of failures when they occur.

Figure 17-11 Margin

Oct 4/02 17-11

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.10 Fbmap
Fbmap displays failure data stored in the AFM using a bit-map.
It is an effective tool for analyzing or evaluating memory devices.

Figure 17-12 Fbmap

17.3.11 ALGP Tool

ALGPTool is used to display and modify the register values of ALPG in the vector files (Link, and
Scramble) transferred to the pattern generator.

17.3.12 Mtrace
Mtrace is the pattern program debugger that displays the output signals from the ALPG for each
step of the ALPG pattern program.

17.3.13 Wavescope
This tool can display measured analog data and perform arithmetic operations on it (e.g., FFT).

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.3 Tools

17.3.14 Wafer Map

Wafer Map is a tool that allows you to display pass/fail and bin results of dies on the wafer. Wafer
Map displays pass, fail percentage for the lot of wafers.

Figure 17-13 Wafer Map

17.3.15 Summary
Summary is a tool that allows you to display the sort count and category count.

17.3.16 TDL Debugger

TDL Debugger is a tool that allows you to debug a TDL test plan program.
With TDL Debugger, you can edit, compile, and control the TDL test plan program.

17.3.17 Mask Tool

Mask tool can set the region of pattern addresses where data comparison is performed when the
pattern program is executed. Using this tool, whether or not to perform data comparison for the
specified pins can also be set. Mask tool allows you to perform data comparison for the specified
pins and address region without changing the current pin condition and pattern data.

Oct 4/02 17-13

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.4 Linking of Tools

17.4 Linking of Tools

Viewpoint has links between tools.
To easily obtain detailed data, Viewpoint can execute another tool from one tool.
This function improves evaluation and analysis efficiency.
Figure 17-14 shows an example of analyzing DUT failures using linked tools.
Patview selects a specific range, and Latool or OSCtool checks the DUT I/O conditions in the se-
lected range.

Patview executes OSCtool.

Patview executes Latool.

Latool executes OSCtool.

Figure 17-14 Inter-tool Link from Patview

17-14 Oct 4/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

17.5 Viewpoint Online Manual

17.5 Viewpoint Online Manual

Viewpoint includes a Viewpoint online manual that can display information on programming and op-
eration in the workstation screen.
The Viewpoint online manual links between the table of contents, index, and text body, allowing
you to simply search the manual for desired information at the device evaluation and mass produc-
tion site.

17.6 Vsim (Option)

Vsim is a software-based tester hardware simulator.
It enables test flow control debugging by test program execution, runtime error detection, and test
results in advance.
Vsim can also check the test system timing restrictions.
Because Vsim can debug test programs without use of an actual tester, the tester can be used
more effectively to shorten TAT for test program development.

Oct 4/02 17-15

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18. INSTALLATION

18. INSTALLATION

18.1 Operating Environment

To ensure that the T6573, T6563, or T6533 operates according to specifications, make sure the
operating environment conforms to the conditions listed below.

Table 18-1 Operating Environment

Temperature Operating 25 °C ± 5 °C
Changes must not exceed 2 °C/hour.
Not operating - 20 °C to 60 °C
Relative Operating 40% to 65%
humidity Not operating 20% to 90%
Vibration Operating 0.2 g or less (5 Hz to 50 Hz)
Not operating 0.5 g or less (50 Hz to 500 Hz)
Shock Not operating 3 g or less
Atmosphere The ambient atmosphere must be free of
salinity, iron, or corrosive gases.
Dust 0.1 mg/m3 or less

Note: No printer must be installed in the clean room.

18.2 Calibration
The T6573, T6563, and T6533 acquire system timing adjustment data before calibration of the test
system. The acquired data is transferred when a device is tested.
The T6573, T6563, and T6533 also provide TDR calibration, which adjusts the delay time caused
by the wire length of the performance board or probe card.
The timing accuracy is ensured for six months unless a board is replaced.
To ensure test reliability and accuracy, the T6573, T6563, and T6533 use a dedicated calibration
board for acquiring timing adjustment data. The calibration board is used to acquire timing skew
adjustment data for the driver and comparator of an I/O pin. To acquire the adjustment data, install
the calibration board on the test head, and use the menu in the Viewpoint console window.

Dec 10/03 18-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.3 Power Supply

18.3 Power Supply

18.3.1 Power Supply Requirements
Use a power supply that satisfies the following requirements.
Table 18-2 Power Supply Requirements
Voltage 3-phase 180 V AC to 220 V AC
Current 50 A
Frequency 50 Hz ±0.5%/60 Hz ±0.5%
Number of systems 1
Ground resistance Less than 100 Ω
Lightening serge voltage in common mode 1000 V or Lower
Lightening serge voltage in differential mode 500 V or Lower
Momentum power failure 10 ms or Lower
Fast transient burst voltage 2000 V or Lower
Lightening serge voltage to the interface cable 250 V or Lower
Fast transient burst voltage to the interface cable 1000 V or Lower

Maximum 50 A Mainframe

200 V 3φ

Ground

Figure 18-1 Power Supply Connection

18.3.2 Power Supply Connection

Users must provide power cables for the test system.
Before connecting the power cable, ensure that the conditions listed below are satisfied.
For the power cable connection location, refer to Section 18.5,”Locations at Which AC Power
and Compressed Air are Supplied.”
• Install a leakage detection breaker with a rated sensitivity of 30 mA.
• The dimensions of the crimp contact should be as follows:
Maximum outside diameter: 15 mm.
Set screw hole diameter: 6.4 mm.
• To avoid reversing the direction of the three-phase AC fan, connect the breakers on the
tester side in the order R, S, and T (U, V, and W) from the left side of the operation panel of
the power input terminal.
(Make sure that the air flows from the top of the mainframe.)

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.4 Compressed Air Supply

18.3.3 Power Consumption

The following table shows the power consumption of the T6573, T6563, and T6533.
Options includes the SCPG, ALPG, AD, DA, and DPS.
Table 18-3 Power Consumption

Power consumption
Configuration
Without options With options
256 ch 5.2 kVA 7.4 kVA
512 ch 7.3 kVA 9.5 kVA
* Rated breaking capacity of the main power supply breaker: 30 KA

18.4 Compressed Air Supply

Compressed air is required to operate the HIFIX lock mechanisms of the test head and perfor-
mance board for the T6573, T6563, and T6533.

18.4.1 Compressed Air Requirements

The compressed air supplied to the tester must satisfy the following requirements.
Table 18-4 Compressed Air Requirements
Pressure 4.4 × 105 Pa to 6.8 × 105 Pa
(4.5 kg/cm2 to 7.0 kg/cm2)
Quantity of flow 5 to 10 Nl/minute

18.4.2 Plumbing
An air hose fitting and coupler are provided for connecting compressed air to the test system.
Provide a hose that has an inner diameter of 8 mm, and fit it as shown below.
For the plumbing location, Refer to Section 18.5, “Locations at Which AC Power and Com-
pressed Air are Supplied.”

Provided by the user Provided with the system

Figure 18-2 Air Hose Connection

Dec 10/03 18-3

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.5 Locations at Which AC Power and Compressed Air are Supplied

18.5 Locations at Which AC Power and Compressed Air are Supplied

Connected location of power supply cable

AIR CONT

Regulator
Connected position
of air hose

Figure 18-3 Locations where AC Power Supply and Air Hose are Connected (REAR View)

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.6 Heat Consumption and Ventilation in the Test System

18.6 Heat Consumption and Ventilation in the Test System

The T6573, T6563, and T6533 exhaust heat and air at the rates shown below.
Note these values when providing air-conditioning around the tester.

18.6.1 Heat Consumption

The following table shows the Heat Consumption of the T6573, T6563, and T6533.
Options includes the SCPG, ALPG, AD, DA, and DPS.

Table 18-5 Heat Consumption

Heat Consumption
Configuration
Without options With options
256 ch 16000 kJ/h 22800 kJ/h
512 ch 22500 kJ/h 29200 kJ/h

18.6.2 Ventilation
The following table shows the airflow rates of the T6573, T6563, and T6533.

Table 18-6 Ventilation Airflow

Unit Airflow
Mainframe 8 m3/min
Test head 24 m3/min

The mainframe airflow can be set to either upwards or downwards.

The test head air intake can be set to the front or the back.

Sep 29/00 18-5

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.6 Heat Consumption and Ventilation in the Test System

18.6.3 Fan Location

Exhausted Air : 8m3/min

Figure 18-4 Mainframe Fan Location

18-6 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.6 Heat Consumption and Ventilation in the Test System

Exhausted Air : 8m3/min

Exhausted Air : 4m3/min

Figure 18-5 Test Head Fan Location

Sep 29/00 18-7

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

18.7 Floor Plan

Figure 18-6 to Figure 18-14 show the floor plans for manual testing, testing with a wafer prober con-
nected, and testing with a handler connected.
The range of movement of each section is shown in Table 18-7.

Table 18-7 Range of Movement

Base point Range (cable length)

Test head Mainframe 5m *1
4.5 m *2
External monitor Mainframe 7.5 m
External TC7 expansion frame Mainframe 5m

*1: The test head cable is led out from the front of the mainframe.
*2: The test head cable is led out from the back of the mainframe.

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-6 Floor Plan for Manual Test (Built-in Monitor)

Sep 29/00 18-9

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-7 Floor Plan for Manual Test (External Monitor)

18-10 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-8 Floor Plan for Manual Test (External Monitor TC7 Installation)

Dec 10/03 18-11

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-9 Floor Plan for Handler (M4541A) Connection (Built-in Monitor)

18-12 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-10 Floor Plan for Handler (M4541A) Connection (External Monitor)

Dec 10/03 18-13

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-11 Floor Plan for Handler (M4541A) Connection (External Monitor TC7 Installation)

18-14 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-12 Floor Plan for Wafer Prober Connection (Built-in Monitor)

Dec 10/03 18-15

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-13 Floor Plan for Wafer Prober Connection (External Monitor)

18-16 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.7 Floor Plan

Figure 18-14 Floor Plan for Wafer Prober Connection (External Monitor TC7 Installation)

Dec 10/03 18-17

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.8 Weight

18.8 Weight
Table 18-8 lists the weight of the system components.
Figure 18-15 to Figure 18-18 show the locations of the mainframe, test head, and monitor desk
jacks.

Table 18-8 Weight of T6573, T6563, and T6533 Components

System component Weight

Mainframe (with a built-in monitor) 350 kg
256 pins 190 kg
Test head unit
512 pins 220 kg
256 pins 230 kg
Test head + Test head stand (for Manual)
512 pins 260 kg
256 pins 320 kg
Test head + Test head stand (for Handler)
512 pins 350 kg
Monitor desk + monitor + keyboard 50 kg
External TC7 expansion frame + monitor + keyboard 110 kg

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 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.8 Weight

Figure 18-15 Location of Mainframe Jacks

Dec 10/03 18-19

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.8 Weight

Figure 18-16 Location of Test Head Jacks

Figure 18-17 Location of Monitor Desk Jacks

18-20 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.8 Weight

Figure 18-18 Location of the External TC7 Expansion Frame Jacks

Dec 10/03 18-21

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.9 Earthquake Protection Measures

18.9 Earthquake Protection Measures

As a safeguard in the event of an earthquake, ADVANTEST provides equipment (optional) that se-
cures the test system to the floor.
Before anchoring the test system to the floor with bolts, a consultation is required.
Figure 18-19 shows how to position the equipment.

18-22 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.9 Earthquake Protection Measures

Figure 18-19 Location of Earthquake Protection Equipment

Dec 10/03 18-23

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

18.9 Earthquake Protection Measures

Figure 18-20 Location of Earthquake Protection Equipment (External Monitor TC7 Installation)

18-24 Dec 10/03

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

19. REPLACEMENT OF LIMITED LIFE PARTS

19. REPLACEMENT OF LIMITED LIFE PARTS

To ensure stable operation of the system, limited life parts must be replaced within the life periods
shown below.
Note that parts may need to be replaced earlier than the times indicated depending on the operat-
ing environment or frequency of use.

Table 19-1 Limited Life Parts

Part name Service life Remarks

Unit power supply 5 years Including the capacitor
Fan motor 5 years
Electrolytic capacitor 5 years
LCD 6 years
LCD backlight 50,000 hours
CD driver 5 years
FDD 5 years
CRT display 5 years
Pilot lamp 6 months Always on
Pogo pin 200,000 times
ZIF connector 20,000 times
HFZIF connector 50,000 times
LIF connector 10,000 times
Gas spring 1 year
Air Coupler 3 years
CD-RW drive About 10 years TC7-equipped system
Battery About 5 years
CPU power supply About 5 years Including the capacitor

Dec 10/03 19-1

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

20. LIMITED WARRANTY AND CUSTOMER SERVICE

20. LIMITED WARRANTY AND CUSTOMER SERVICE

20.1 Limited Warranty

(1) Unless otherwise specifically agreed by Seller and Purchaser in writing, ADVANTEST will
warrant to the Purchaser that during the Warranty Period this test system (other than
consumables included in the test system) will be free from defects in material and
workmanship and shall conform to the specifications set forth in this Product Description.

(2) The warranty period for the test system (the “Warranty Period”) will be a period of one year
commencing on the date that the test system has been accepted under and in accordance
with the Terms and Conditions of Sale.

(3) If the test system is found to be defective during the Warranty Period, ADVANTEST will, at
its option and in its sole and absolute discretion, either (a) repair the defective test system
or part or component thereof or (b) replace the defective test system or part or component
thereof, in either case at ADVANTEST’s sole cost and expense.

(4) This limited warranty (and all of ADVANTEST’s obligations with respect thereto) will
terminate and be void in the event that, without ADVANTEST’s prior written consent, (a)
the test system is moved from its original installation site or (b) the test system is sold or
transferred by the Purchaser to a third party.

(5) This limited warranty will not apply to defects or damage to the test system or any part or
component thereof resulting from any of the following:
(a) any modifications, maintenance or repairs other than modifications, maintenance or
repairs (i) performed by ADVANTEST or (ii) specifically recommended or authorized by
ADVANTEST and performed in accordance with ADVANTEST’s instructions;

(b) any improper or inadequate handling, carriage or storage of the test system by the
Purchaser or any third party (other than ADVANTEST or its agents);

(c) use of the test system under operating conditions or environments different than those
specified in the Product Description or the operation manual or recommended by
ADVANTEST, including, without limitation, (i) instances where the test system has been
subjected to physical stress or electrical voltage exceeding the permissible range and (ii)
instances where the corrosion of electrical circuits or other deterioration was accelerated
by exposure to corrosive gases or dusty environments;
(d) use of the test system in connection with software, interfaces, products or parts other
than software, interfaces, products or parts supplied or recommended by ADVANTEST;

(e) the occurrence of an event of force mature, including, without limitation, fire, explosion,
geological change, storm, flood, earthquake, tidal wave, lightning or act of war; or

(f) any negligent act or omission of the Purchaser or any third party other than
ADVANTEST.

Sep 27/01 20-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

20.1 Limited Warranty

(6) EXCEPT TO THE EXTENT EXPRESSLY PROVIDED HEREIN, ADVANTEST HEREBY

EXPRESSLY DISCLAIMS, AND THE PURCHASER HEREBY WAIVES, ALL
WARRANTIES, WHETHER EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE,
INCLUDING, WITHOUT LIMITATION, (A) ANY WARRANTY OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE AND (B) ANY WARRANTY OR
REPRESENTATION AS TO THE VALIDITY, SCOPE, EFFECTIVENESS OR
USEFULNESS OF ANY TECHNOLOGY OR ANY INVENTION.

(7) THE REMEDY SET FORTH HEREIN SHALL BE THE SOLE AND EXCLUSIVE REMEDY
OF THE PURCHASER FOR BREACH OF WARRANTY WITH RESPECT TO THE TEST
SYSTEM.

(8) ADVANTEST WILL NOT HAVE ANY LIABILITY TO THE PURCHASER FOR ANY
INDIRECT, INCIDENTAL, SPECIAL, CONSEQUENTIAL OR PUNITIVE DAMAGES,
INCLUDING, WITHOUT LIMITATION, LOSS OF ANTICIPATED PROFITS OR
REVENUES, IN ANY AND ALL CIRCUMSTANCES, EVEN IF ADVANTEST HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES AND WHETHER ARISING OUT
OF BREACH OF CONTRACT, WARRANTY, TORT (INCLUDING, WITHOUT
LIMITATION, NEGLIGENCE), STRICT LIABILITY, INDEMNITY, CONTRIBUTION OR
OTHERWISE.

20-2 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

20.2 Customer Service Description

20.2 Customer Service Description

In order to maintain safe and trouble-free operation of the test system and to prevent the incurrence
of unnecessary costs and expenses, ADVANTEST recommends a regular preventive maintenance
program under its maintenance agreement.

ADVANTEST’s maintenance agreement provides the Purchaser on-site and off-site maintenance,
parts, maintenance machinery, regular inspections, and telephone support and will last a maximum
of ten years from the date the Purchaser accepts delivery of the test system. For specific details of
the services provided under the maintenance agreement, please contact the nearest ADVANTEST
office.

Some of the components and parts of this test system have a limited operating life (such as, elec-
trical and mechanical parts, fan motors, unit power supply, etc.). Accordingly, these components
and parts will have to be replaced on a periodic basis. If the operating life of a component or part
has expired and such component or part has not been replaced, there is a possibility that the test
system will not perform properly. Additionally, if the operating life of a component or part has ex-
pired and continued use of such component or part damages the test system, the test system may
not be repairable. The operating life may vary depending on various factors such as operating con-
dition and usage environment. For more information, contact the nearest ADVANTEST office.

Sep 27/01 20-3

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

21. ACCEPTANCE TEST AND INSTALLATION

21. ACCEPTANCE TEST AND INSTALLATION

21.1 Acceptance Test

An acceptance test is performed immediately before shipment of the T6573, T6563, or T6533 from
the factory to check that:

(1) The system configuration conforms to the approved work instructions (individual manufac-
turing specifications).

(2) System performance is as stated in the test records.

(3) The system diagnostic results from the self-diagnostic program are acceptable.
The self-diagnostic is performed on a system under test that has been active for at least 30
minutes after power-on.

(4) The delivery conditions and installation environment are acceptable.

A check is made to determine if there will any problems (for example, obstacles along the
delivery route. The system installation environment and installation layout are also
checked.
If any acceptance test item or procedure not described in (1) to (4) above is required, inform us
before the acceptance test so that we can include it in the acceptance test. An additional fee may
be required.

21.2 Installation
Our personnel perform the installation. The customer is responsible for power supply connections.
Installation consists of the following steps:

(1) Delivery to the designated location

(2) Power connection, assembly, and adjustment

(3) Verification that installation is complete

Installation is assumed to have been completed when the customer and ADVANTEST have ex-
changed a "Confirmation of Completion of Installation" form.
The customer should check the following items regarding the delivery route from the point of un-
loading to the installation site:

(1) The main unit and test head stand can pass with no problem.

(2) The floor is strong enough to bear the weight.

(3) The elevator can accommodate the main unit and test head stand.

(4) The floor is level and has no gaps or openings.

(5) The route is not exposed to rain, dust, or corrosive gases.

If it is not possible to meet these conditions, consult ADVANTEST before delivery.

Sep 29/00 21-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

21.2 Installation

The installation site must meet the requirements described in Section 18, "INSTALLATION." Instal-
lation is performed based on the layout specified in individual manufacturing specifications.
The customer is asked to make sure that power supply connections will be completed within one
hour after the system is delivered.
Completion of installation will be verified based on the same items and according to the same pro-
cedure as those described in Section 21.1, "Acceptance Test." Installation and acceptance inspec-
tion are assumed to have been completed when the verification of installation completion
procedure has been completed.

21-2 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22. SPECIFICATIONS

22. SPECIFICATIONS

22.1 System Specifications

Item Specification Remarks

OS Viewpoint
Number of stations 1
HIFIX 512pogoHIFIX Using 512-channel PB
512ZIFHIFIX Using 1024-channel PB
512AV2HIFIX Using T6672 AV2HIFIX PB
512SQHIFIX Using SQ HIFIX PB
Use one of the above types of HIFIX.
I/O pin 256 pin(Min)
512 pin(Max) Expandable in 256-pin increments
Number of parallel tests 8 DUT(Max) Minimum group of pins: 64 pins/DUT
Maximum oper- T6573 PMUX or PTMUX: 250 MHz
125 MHz
ating frequency PMUX and PTMUX: 500 MHz
T6563 PMUX or PTMUX: 125 MHz
62.5 MHz
PMUX and PTMUX: 250 MHz
T6533 PMUX or PTMUX: 62.5 MHz
31.25 MHz
PMUX and PTMUX: 125 MHz
Timing edge 6 TE/pin
Overall timing accuracy ±500 ps
Driver skew ±200 ps
Comparator skew ±200 ps
SQPG 16 MW × 3 bit/pin
Option.
64 MW × 3 bit/pin
Use either of 16 MW and 64 MW.
DFM 256 W × 2 bit/pin
DPS 2 A × 8 ch (Min)
Option. Expandable in 8-channel incre-
ments
The number of usable channels varies
2 A × 32 ch (Max)
depending on the HIFIX.
For more information, refer to Chapter
9.
UDC 4 Assignment to pins: 128 pins/unit
MDC 16 (Min) 16 pin/unit
32 (Max)
CPU TC4
Control panel 1 Option

Nov 8/02 22-1

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.1 System Specifications

Item Specification Remarks

ALPG option X: 16, Y: 16, Data: 32
Control signal: 18
SCPG option 4 G × 2 bit/pin
16 G × 2 bit/pin
AFM option (32 MW × 1 bit to
STORE only
1 MW × 36 bit)/128 pin
Analog option ADC 16 bit × 4 ch
Waveform
memory 256 kW
DCAP 256 kW × 32 bit × 1 ch
DAC 16 bit × 4 ch
Waveform
capture 256 kW
memory
REF power
8 ch VRH 4 ch, VRL 4 ch
supply
MTX 16 ch
HRS option 72 Gbyte(Min)
Extended in units of 72 GB
504 Gbyte(Max)

*: W in a unit in the table represents words.

22-2 Nov 8/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.2 Timing Specifications

22.2 Timing Specifications

Item Specification
Timing edge 6 TE/pin
Minimum rate T6573 8 ns
T6563 16 ns
T6533 32 ns
Maximum rate 1 ms
Rate setting resolution 31.25 ps
Number of timing sets 32
Maximum edge delay time 4 x rate - 8 ns or (16 µs max.)
Edge setting resolution 31.25 ps
Proximity between timing edges that are the same 8 ns
Proximity between different timing edges 8 ns (*1)

*1: For the proximity between different timing edges, the following restrictions between
SET and SET or between RESET and RESET apply:

(1) When RESET is inserted between SET and SET of different timing edges

Tm Tn
8ns

Figure 22-1 When RESET is Inserted between SET and SET of Different Timing Edges

(2) When SET is inserted between RESET and RESET of different timing edges

Tm Tn
8ns

Figure 22-2 When SET is Inserted between RESET and RESET of Different Timing Edges

However, no restrictions apply to the proximity between different timing edges in the follow-
ing cases:
• A double clock or FNRZ is used.
• RESET is not inserted between SET and SET.
• SET is not inserted between RESET and RESET.

Sep 29/00 22-3

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.3 Driver Specifications

22.3 Driver Specifications

Item Specification
Driver transition time 1.2±0.25 ns at 0 V-3 V(20%-80%)
Minimum pulse width 4.0 ns/3 Vp-p, 2.0 ns/1 Vp-p
Output voltage amplitude 0.2 V to 8.0 Vp-p
Output voltage range VIH=-1.8 V to 6.0 V
VIL=-2.0 V to 5.0 V
Output voltage accuracy ±(1.0% + 20 mV)
Output voltage resolution 2 mV
DC output current resolution ±40 mA
Output impedance 50 Ω±5 Ω
Overshoot ±(amplitude × 5% + 50 mV)
Driver skew ±200 ps
I/O switching timing accuracy HIZ mode ±500 ps (Note 1)
VTT mode ±400 ps (Note 2)
DRE minimum on/off time ON time OFF time
HIZ mode 8.0 ns 8.0 ns
VTT mode 4.0 ns 4.0 ns

3V
2.5 V
1.5 V
0.5 V Note 1: Designated DRE timing in HIZ mode
0V
DR OFF DR ON

2.25 V 2.0 V
1.5 V
1.5 V, 50 Ω termination
0.75 V 1.0 V
Note 2: Designated DRE timing in VTT mode
DR OFF DR ON

Digital Scope
Test station Performance board
450 Ω
DR
Zo = 50 Ω
50 Ω
Tpd = 1 ns

Figure 22-3 Driver Loading Conditions

22-4 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.4 Comparator Specifications

22.4 Comparator Specifications

Item Specification
Comparator transition time HIZ mode 1.2 ns or less at 0 V to 3 V (20-80%)
VTT mode 1.0 ns or less at 0 V to 1 V (20-80%)
Input comparison voltage range VOH/VOL -2.0 V to +6.0 V
Input comparison voltage resolution 2 mV
Input comparison voltage accuracy ±(1.0% + 20 mV)
Edge comparator skew ±200 ps
Window strobe minimum glitch detection width 2.5 ns
Minimum window strobe on time 4.0 ns
Minimum window strobe off time 6.0 ns
Window comparator skew ±500 ps
Leakage current ±600 nA

I/O dead band

HIFIX
(includes a 1.0 ns wire length on PB)
512pogoHIFIX 8.3 ns
512ZIFHIFIX 8.1 ns
512AV2HIFIX 8.3 ns
512SQHIFIX 10.1 ns

Nov 8/02 22-5

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.5 Terminator Specifications

22.5 Terminator Specifications

Item Specification
Resistance accuracy 50 Ω±5 Ω
VTT voltage range -2.0 V to +6.0 V
VTT voltage accuracy ±(1.0% + 20m V)
VTT voltage resolution 2 mV
VTT maximum current ±40 mA
Allowable input voltage range -2.0 V ≤ input voltage - VTT ≤ 2.0 V

22.6 Programmable Load Specifications

Item Specification
Current range IL: 0 mA to 24 mA
IH: 0 mA to -24 mA
Current accuracy ±(4.0% + 100 µA)
Current resolution 20 µA
Threshold voltage range -2.0 V to 6.0 V
Threshold voltage accuracy ±(1.0% + 200 mV)
Threshold voltage resolution 2 mV
Minimum ON time 8 ns
Minimum OFF time 8 ns

22.7 Dynamic Clamp Specifications

Item Specification
Clamp voltage range DCLP: -0.8 V to 6.0 V
(When Clamp current is 2 mA)
DCLM: -2.0 V to 2.0 V
(When Clamp current is 2 mA)
Clamp setup width (DCLP-DCLM) 0.5 V to 8.0 V
Clamp voltage accuracy ±(5.0% + 200 mV)
(When Clamp current is 2 mA)
Clamp voltage resolution 16 mV
Maximum clamp current ±20 mA
DCLP and DCLM are subject to the following limitations with respect to VIH, VIL, and VT:
DCLM ≤ VIL < VIH < DCLP
DCLM ≤ VTH ≤ DCLP

22-6 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.8 Multi-DC Unit Specifications

22.8 Multi-DC Unit Specifications

22.8.1 Voltage Source Current Measurement (VSIM)

Voltage source
Voltage Setting Maximum
Resolution Setting Accuracy
Range Range Current
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA) ±60 mA

Current measurement

Measurement Current
Current Range Resolution Measurement Accuracy
Range Limitation
8 µA 0 to ±6 µA 2 nA ±(0.5%+ 6nA+1 nA/V) 0.999 mA
80 µA 0 to ±60 µA 20 nA ±(0.2%+40 nA+10 nA/V) 0.999 mA
800 µA 0 to ±600 µA 200 nA ±(0.2%+400 nA+100 nA/V) 0.999 mA
8 mA 0 to ±6 mA 2 µA ±(0.2%+4 µA+1 µA/V) 6.0273 mA
80 mA 0 to ±60 mA 20 µA ±(0.5%+60 µA+10 µA/V) 60.273 mA

Settling time

Voltage Range Current Range Settling Time (99% or more of full scale)
8 µA 10.0 ms
80 µA 2.0 ms
8V 800 µA 0.5 ms
8 mA 0.5 ms
80 mA 0.5 ms

Load: R + C (100 pF)

Maximum load capacitance

1000 pF

Sep 29/00 22-7

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.8 Multi-DC Unit Specifications

22.8.2 Current Source Voltage Measurement (ISVM)

Current source
Setting Maximum
Current Range Resolution Setting Accuracy
Range Voltage
80 µA 0 to ±60 µA 20 nA ±(0.2%+20 nA+100 nA/V) -6 V to 8 V
800 µA 0 to ±600 µA 200 nA ±(0.2%+200 nA+1 µA/V) -6 V to 8 V
8 mA 0 to ±6 mA 2 µA ±(0.2%+2 µA+10 µA/V) -6 V to 8 V
80 mA 0 to ±60 mA 20 µA ±(0.5%+40 µA+100 µA/V) -6 V to 8 V

Voltage measurement

Measurement
Voltage Range Resolution Measurement Accuracy
Range
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA)

Voltage limitations (positive and negative)

Range of Positive Range of Negative Setting
Voltage Range Resolution
Voltages Voltages Accuracy
8V 42.6 mV 340.8 mV to 8.307 V -(340.8 mV to 6.3048 V) ±0.3 V

Settling time
Current Range Voltage Range Settling Time (99% or more of full scale)
80 µA 3.0 ms
800 µA 1.0 ms
8V
8 mA 0.5 ms
80 mA 0.5 ms
Load: R + C (100 pF)
Maximum load capacitance
1000 pF

22-8 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.8 Multi-DC Unit Specifications

22.8.3 Voltage Measurement (MVM)

Voltage measurement

Measurement
Voltage Range Resolution Measurement Accuracy
Range
8V -6 V to 8 V 2 mV ±(0.1%+4 mV)

Input impedance
10 MΩ or greater

Sep 29/00 22-9

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9 Universal DC Unit

22.9.1 Voltage Source Current Measurement (VSIM) during Dedicated Terminal
Output

Voltage source

Voltage Setting Maximum

Resolution Setting Accuracy
Range Range Current
2V -2 V to 2 V 0.5 mV ±(0.1%+2 mV+2 mV/10 mA) ±300 mA
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA) ±300 mA
40 V -40 V to 40 V 10 mV ±(0.1%+20 mV) ±8 mA

Current measurement

Current Measurement Voltage

Resolution Measurement Accuracy
Range Range Limitation
8 µA 0 to ±8 µA 2 nA ±(0.5%+6 nA+1 nA/V) -6 V to 8 V
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V) -6 V to 8 V
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V) -40 V to 40 V
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V) -40 V to 40 V
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V) -6 V to 8 V
300 mA 0 to ±300 mA 200 µA ±(0.5%+500 µA+100 µA/V) -6 V to 8 V

Current limitations (positive and negative)

Current Range Setting Range Resolution Setting Accuracy

8 µA ±10.24 µA* — ±(15%+200 nA)
80 µA ±102.4 µA* — ±(15%+2 µA)
800 µA ±1.024 mA* — ±(15%+20 µA)
8 mA 0 to ±10.24 mA 64 µA ±(15%+200 µA)
80 mA 0 to ±102.4 mA 640 µA ±(15%+2 mA)
300 mA 0 to ±345.6 mA 6.4 mA ±(15%+20 mA)
*: Fixed

22-10 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

Settling time

Voltage Range Current Range Settling Time (99% or more of full scale)
8 µA 2.0 ms
80 µA 1.0 ms
800 µA 1.0 ms
2V
8 mA 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms
8 µA 3.5 ms
80 µA 1.0 ms
800 µA 1.0 ms
8V
8 mA 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms
800 µA 1.0 ms
40 V
8 mA 1.0 ms
Load: R + C (100 pF)
Maximum load capacitance
1000 pF

Sep 29/00 22-11

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.2 Current Source Voltage Measurement (ISVM) during Dedicated Terminal

Output

Current source

Current Maximum
Setting Range Resolution Setting Accuracy
Range Voltage
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V) -6 V to 8 V
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V) -40 V to 40 V
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V) -40 V to 40 V
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V) -6 V to 8 V
300 mA 0 to ±300 mA 200 µA ±(0.5%+500 µA+100 µA/V) -6 V to 8 V

Voltage measurement

Measurement
Voltage Range Resolution Measurement Accuracy
Range
2V -2 V to 2 V 0.5 mV ±(0.1%+2 mV+2 mV/10 mA)
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA)
40 V -40 V to 40 V 10 mV ±(0.1%+20 mV)

Voltage limitations (positive and negative)

Range of Positive Range of Negative Setting

Voltage Range Resolution
Voltages Voltages Accuracy
2V 256 mV 512 mV to 2.560 V -(512 mV to 2.560 V) ±1 V
8V 256 mV 512 mV to 10.24 V -(512 mV to 7.168 V) ±1 V
40 V 256 mV 512 mV to 41.984 V -(512 mV to 41.984 V) ±1 V

22-12 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

Settling time

Current Range Voltage Range Settling Time (99% or more of full scale)
80 µA 1.0 ms
800 µA 1.0 ms
8 mA 2V 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms
80 µA 1.5 ms
800 µA 1.0 ms
8 mA 8V 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms
800 µA 1.5 ms
40 V
8 mA 1.0 ms
Load: R + C (100 pF)

Maximum load capacitance

1000 pF

Sep 29/00 22-13

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.3 Voltage Measurement (MVM) during Dedicated Terminal Output

Voltage source
Measurement
Voltage Range Resolution Measurement Accuracy
Range
2V -2 to 2 V 0.5 mV ±(0.1%+2 mV)
8V -6 V to 8 V 2 mV ±(0.1%+4 mV)
40 V -40 V to 40 V 10 mV ±(0.1%+20 mV)

Input impedance
10 MΩ or greater

22-14 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.4 Voltage Source Current Measurement (VSIM) when MDC Interruption

Voltage source

Voltage Setting Maximum

Resolution Setting Accuracy
Range Range Current
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA) ±128 mA

Current measurement
Current Measurement Voltage
Resolution Measurement Accuracy
Range Range Limitation
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V) -6 V to 8 V
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V) -6 V to 8 V
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V) -6 V to 8 V
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V) -6 V to 8 V
300 mA 0 to ±128 mA 200 µA ±(0.5%+500 µA+100 µA/V) -6 V to 8 V

Current limitations (positive and negative)

Current Range Setting Range Resolution Setting Accuracy

80 µA ±102.4 µA* — ±(15%+2 µA)
800 µA ±1.024 mA* — ±(15%+20 µA)
8 mA 0 to ±10.24 mA 64 µA ±(15%+200 µA)
80 mA 0 to ±102.4 mA 640 µA ±(15%+2 mA)
300 mA 0 to ±160 mA 6.4 mA ±(15%+20 mA)
*: Fixed

Settling time

Voltage Range Current Range Settling Time (99% or more of full scale)
80 µA 2.5 ms
800 µA 1.5 ms
8V 8 mA 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms

Load: R + C (100 pF)

Maximum load capacitance
1000 pF

Sep 29/00 22-15

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.5 Current Source Voltage Measurement (ISVM) during MDC Interruption

Current source
Current Setting Maximum
Resolution Setting Accuracy
Range Range Voltage
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V) -6 V to 8 V
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V) -6 V to 8 V
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V) -6 V to 8 V
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V) -6 V to 8 V
300 mA 0 to ±128 mA 200 µA ±(0.5%+500 µA+100 µA/V) -6 V to 8 V

Voltage measurement
Measurement
Voltage Range Resolution Measurement Accuracy
Range
2V -2 V to 2 V 0.5 mV ±(0.1%+2 mV+2 mV/10 mA)
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+2 mV/10 mA)

Voltage limitations (positive and negative)

Voltage Range of Positive Range of Negative Setting

Resolution
Range Voltages Voltages Accuracy
2V 256 mV 512 mV to 2.560 V -(512 mV to 2.560 V) ±1 V
8V 256 mV 512 mV to 10.24 V -(512 mV to 7.168 V) ±1 V

Settling time

Current Range Voltage Range Settling Time (99% or more of full scale)
80 µA 1.5 ms
800 µA 1.0 ms
8 mA 8V 1.0 ms
80 mA 1.0 ms
300 mA 1.0 ms
Load: R + C (100 pF)
Maximum load capacitance
1000 pF

22-16 Sep 29/00

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.6 Voltage Source Current Measurement (VSIM) when Connected to

Converters Option
UDC can be connected to Converters option, and VSIM measurement is possible.

Voltage settings

Range of Maximum
Voltage Range Resolution Setting Accuracy
Settings Current
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+8 mV/10 mA) ±128 mA

Current measurement

Range of Maximum
Current Range Resolution Measurement Accuracy
Measurements Voltage
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V) -6 V to 8 V
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V) -6 V to 8 V
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V) -6 V to 8 V
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V) -6 V to 8 V
300 mA 0 to ±128 mA 200 µA ±(0.5%+500 µA+100 µA/V) -6 V to 8 V

Current limitations (positive and negative)

Range of
Current Range Resolution Setting Accuracy
Settings
80 µA ±102.4 µA — ±(15%+2 µA)
800 µA ±1.024 mA — ±(15%+20 µA)
8 mA 0 to ±10.24 mA 64 µA ±(15%+200 µA)
80 mA 0 to ±102.4 mA 640 µA ±(15%+2 mA)
300 mA 0 to ±160 mA 6.4 mA ±(15%+20 mA)

Maximum load capacitance

1000 pF

Sep 27/01 22-17

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.9 Universal DC Unit

22.9.7 Current Source Voltage Measurement (ISVM) when Connected to

Converters Option
UDC can be connected to Converters option, and ISVM measurement is possible.

Programmable current

Range of
Current Range Resolution Setting Accuracy
Settings
80 µA 0 to ±80 µA 20 nA ±(0.2%+40 nA+10 nA/V)
800 µA 0 to ±800 µA 200 nA ±(0.2%+400 nA+100 nA/V)
8 mA 0 to ±8 mA 2 µA ±(0.2%+4 µA+1 µA/V)
80 mA 0 to ±80 mA 20 µA ±(0.5%+50 µA+10 µA/V)
300 mA 0 to ±128 mA 200 µA ±(0.5%+500 µA+100 µA/V)

Voltage measurement

Range of
Voltage Range Resolution Measurement Accuracy
Measurements
8V -6 V to 8 V 2 mV ±(0.1%+4 mV+5 mV/10 mA)

Voltage limitations (positive and negative)

Range of Positive Range of Negative Setting

Voltage Range Resolution
Voltages Voltages Accuracy
8V 256 mV 512 mV to 10.24 V -(512 mV to 7.168 V) ±1 V

Maximum load capacitance

1000 pF

22-18 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.10 Device Specifications

22.10 Device Specifications

22.10.1 Voltage Source Current Measurement (VSIM)

Voltage source

Voltage Setting
Resolution Setting Accuracy Maximum Current
Range Range
-6 to 6 V ±500 mA
8V 2 mV ±(0.1%+4 mV)
-6 to 8 V ±2 A

Current measurement
Maximum
Current Measurement Maximum
Resolution Load Measurement Accuracy
Range Range Current
Capacitance
8 µA 0 to ±5 µA 2 nA 1 µF ±(1%+8 nA+2 nA/V) 500 mA
80 µA 0 to ±50 µA 20 nA 1 µF ±(0.2%+80 nA+20 nA/V) 500 mA
800 µA 0 to ±500 µA 200 nA 1 µF ±(0.2%+800 nA+200 nA/V) 500 mA
8 mA 0 to ±5 mA 2 µA 1 µF ±(0.2%+8 µA+2 µA/V) 500 mA
80 mA 0 to ±50 mA 20 µA 1 µF ±(0.5%+80 µA+20 µA/V) 500 mA
800 mA 0 to ±500 mA 200 µA 33 µF ±(0.5%+800 µA+200 µA/V) 500 mA
2A 0 to ±2 A 0.8 mA 33 µF ±(0.5%+8 mA+2 mA/V) 2A

Current limitations (positive and negative)

Current Range Setting Range Resolution Setting Accuracy

8 µA to 800 mA 0 to ±550.4 mA 3.2 mA (5%+20 mA)
2A 0 to ±2.176 A 12.8 mA (5%+200 mA)

Settling time

Voltage Range Current Range Settling Time (99% or more of full scale)
8 µA 10.0 ms
80 µA 3.5 ms
800 µA 2.5 ms
8V 8 mA 1.0 ms
80 mA 1.0 ms
500 mA 1.0 ms
2A 1.0 ms

Load: R

Dec 10/03 22-19

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.10 Device Specifications

22.10.2 Current Measurement during Parallel Operation (VSIM)

Applied voltage
Voltage Range of Maximum Output
Resolution Setting Accuracy
Range Voltage Current
8V -6 to 6 V 2 mV ±(n × 2 A) ±(0.1%+24 mV)
n: Number of units

Current measurement

Current Measurement Measurement Maximum Load

Resolution
Range Range Accuracy Capacitance
±(FSR × 1% +
n×2A 0 to ±(n × 2 A) 0.8 mA n × 33 µF
8 mA × n + 2 mA/V × n)

FSR: Full-scale range (n x 2A)

22.10.3 Voltage Source Voltage Measurement (VSVM)

Voltage source

Maximum
Voltage Setting Setting
Resolution Output Output Impedance
Range Range Accuracy
Current
8V -6 to 8 V 2 mV ±8 mA ±(0.1%+4mV) 1 kΩ±100 Ω

Voltage measurement

Voltage Range Measurement Range Resolution Measurement Accuracy

8V -6 to 8 V 2 mV ±(0.1%+6 mV)

22.10.4 Mean Current Measurement

Sampling speed 100 µs (fixed)

Maximum measurement time 13 s

22-20 Sep 27/01

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.10 Device Specifications

22.10.5 Programmable Slew Rate

Setting Range Resolution

25 µs/1 V to 25 ms/1 V 6.25 µs

1V
V = 64 mV

0V

Setting Range

22.10.6 Overshoot and Undershoot

Connected Load
Current Range RON/ROF Spike
Capacitance
8 µA to 80 mA 1 µF
5% or less of programmed voltage or 0.3
800 mA 33 µF
V whichever is greater
2A 33 µF

22.10.7 Load Fluctuation Characteristics

Fluctuation Load
Current Range Fluctuation Voltage Return time
Current Capacitance
8 µA to 80 mA 0.5 V 0.5 mS 50 mA 1 µF
800 mA 0.1 V 0.5 mS 100 mA 33 µF
2A 0.3 V 0.5 mS 500 mA 33 µF

Fluctuation
voltage

Return Time

Sep 27/01 22-21

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.11 SQPG Specifications

22.11 SQPG Specifications

Item Specification
Normal match
125 MHz
Maximum operating frequency mode
PTMUX 250 MHz
Standard 16 MW
STE
Option 64 MW × 3 bit/pin
VGCS 4 MW
DFM 256 W × 2 bit/pin
Number of overruns after pattern match detected 312 cycles
Rate at which delay match is used (MSTBR + 3.5 µs) or higher

*: W in a unit in the table represents words.

22.12 ALPG Specifications (Option)

Item Specification
Maximum operating frequency 125 MHz
WCS 1 kW
X0 to X15
Address generation
Y0 to Y15
Data generation DA0 to DA17, DB0 to DB17
Control signals R, W, M1 to M2, C0 to C15

*: W in a unit in the table represents words.

22.13 AFM Specifications (Option)

Item Specification
Maximum operating frequency 125 MHz
Memory configuration Maximum size 36 Mbit/28 pin
Bit configuration ×1, ×4, ×9, ×18, ×36
Operation Failure Store
Parallel test configuration Bit configuration ×1 ×4 ×9 ×18 ×36
Number of 512 pin/DUT
pins per 256 pin/DUT 32 MW 8 MW 4 MW 2 MW 1 MW
DUT
128 pin/DUT
64 pin/DUT 16 MW 4 MW 2 MW 1 MW -

22-22 Oct 4/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.14 SCPG Specifications (Option)

22.14 SCPG Specifications (Option)

22.14.1 Scan Pattern Generation

Item Specification
Pattern memory 4G or 16 G
Scan pin 2 pin to 64 pin
Maximum scan file Memory: 4 G 1 GW × 4 pin × 2 bit
address depth Memory: 16 G 4 GW × 4 pin × 2 bit
Maximum operating fre- Scan pins: 2 to 32 125 MHz
quency Scan pins: 48 to 64 62.6 MHz
*: W in a unit in the table represents words.
Scan file address depth
Scan pins Maximum operating frequency
4GSCPG 16GSCPG
1 GW 4 GW 2, 4
512 MW 2 GW 8
125 MHz
256 MW 1 GW 16
128 MW 512 MW 9, 18, 32
64 MW 256 MW 48, 64 62.5 MHz

*: W in a unit in the table represents words.

22.14.2 DAW Pattern Generation

Item Specification
Maximum operating frequency 125 MHz
Capacity 4 G or 16 G
Number of bits 2, 4, 8, 16, 32
Loop count value 24 bit
Number of impulses for which continuous exe-
64
cution is enabled

Oct 4/02 22-23

T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.15 Frequency Measurement Specification

22.15 Frequency Measurement Specification

T6573 Original Frequency: 125 MHz Period: Signal rate to be measured
Range Measurement Range Resolution Accuracy Gate time
M1 ns 200 MHz to 3.726 Hz 1 ns Period* 23
5.0 ns to 268.4 ms
M100 ps 200 MHz to 59.59 Hz 62.5 ps Period* 27
5.0 ns to 16.78 ms
M10 ps 200 MHz to 476.9 Hz 7.8125 ps Period* 210
5.0 ns to 2.097 ms
M1 ps 200 MHz to 3.815 kHz 0.97656 ps Period* 213
±(0.01%+Resolution)
5.0 ns to 262.1 µs
M100 fs 200 MHz to 61.01 kHz 0.06104 ps Period* 217
5.0 ns to 16.39 µs
M10 fs 200 MHz to 488.3 kHz 0.00763 ps Period* 220
5.0 ns to 2.048 µs
M1 fs 200 MHz to 3.906 MHz 0.95367 fs Period* 223
5.0 ns to 0.2560 µs

T6563 Original Frequency: 125 MHz Period: Signal rate to be measured

Range Measurement Range Resolution Accuracy Gate time

M1 ns 200 MHz to 3.726 Hz 1 ns Period* 23
5.0 ns to 268.4 ms
M100 ps 200 MHz to 59.59 Hz 62.5 ps Period* 27
5.0 ns to 16.78 ms
M10 ps 200 MHz to 476.9 Hz 7.8125 ps Period* 210
5.0 ns to 2.097 ms
M1 ps 200 MHz to 3.815 kHz 0.97656 ps Period* 213
±(0.01%+Resolution)
5.0 ns to 262.1 µs
M100 fs 200 MHz to 61.01 kHz 0.06104 ps Period* 217
5.0 ns to 16.39 µs
M10 fs 200 MHz to 488.3 kHz 0.00763 ps Period* 220
5.0 ns to 2.048 µs
M1 fs 200 MHz to 3.906 MHz 0.95367 fs Period* 223
5.0 ns to 0.2560 µs

22-24 Oct 4/02

 T6573/T6563/T6533 VLSI TEST SYSTEM PRODUCT DESCRIPTION

22.15 Frequency Measurement Specification

T6533 Original Frequency: 125 MHz Period: Signal rate to be measured

Range Measurement Range Resolution Accuracy Gate time
M1 ns 200 MHz to 3.726 Hz 1 ns Period* 23
5.0 ns to 268.4 ms
M100 ps 200 MHz to 59.59 Hz 62.5 ps Period* 27
5.0 ns to 16.78 ms
M10 ps 200 MHz to 476.9 Hz 7.8125 ps Period* 210
5.0 ns to 2.097 ms
M1 ps 200 MHz to 3.815 kHz 0.97656 ps Period* 213
±(0.01%+Resolution)
5.0 ns to 262.1 µs
M100 fs 200 MHz to 61.01 kHz 0.06104 ps Period* 217
5.0 ns to 16.39 µs
M10 fs 200 MHz to 488.3 kHz 0.00763 ps Period* 220
5.0 ns to 2.048 µs
M1 fs 200 MHz to 3.906 MHz 0.95367 fs Period* 223
5.0 ns to 0.2560 µs

Oct 4/02 22-25

The information in this document is subject to change without notice.