MX25L12872F

MX25L12872F
3V, 128M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY

Key Features
• Protocol Support - Single I/O, Dual I/O and Quad I/O
• Quad Peripheral Interface (QPI) available
• Supports clock frequencies up to 133MHz
• Program/Erase Suspend and Resume
• Additional 8K-bit secured OTP
• Quad I/O mode is permanently enabled

Macronix Proprietary
 MX25L12872F

Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 5
Table 1. Read performance Comparison.....................................................................................................5
3. PIN CONFIGURATIONS .......................................................................................................................................... 6
4. PIN DESCRIPTION................................................................................................................................................... 6
5. BLOCK DIAGRAM.................................................................................................................................................... 7
6. DATA PROTECTION................................................................................................................................................. 8
Table 2. Protected Area Sizes......................................................................................................................9
Table 3. 8K-bit Secured OTP Definition.....................................................................................................10
7. Memory Organization............................................................................................................................................ 11
Table 4. Memory Organization................................................................................................................... 11
8. DEVICE OPERATION............................................................................................................................................. 12
8-1. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 14
9. COMMAND DESCRIPTION.................................................................................................................................... 15
Table 5. Command Set...............................................................................................................................15
9-1. Write Enable (WREN)............................................................................................................................... 18
9-2. Write Disable (WRDI)................................................................................................................................ 19
9-3. Factory Mode Enable (FMEN).................................................................................................................. 20
9-4. Read Identification (RDID)........................................................................................................................ 21
9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 22
9-6. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 24
9-7. QPI ID Read (QPIID)................................................................................................................................ 25
Table 6. ID Definitions ...............................................................................................................................25
9-8. Read Status Register (RDSR).................................................................................................................. 26
9-9. Read Configuration Register (RDCR)....................................................................................................... 27
Table 7. Status Register.............................................................................................................................30
Table 8. Configuration Register Table........................................................................................................31
Table 9. Output Driver Strength Table........................................................................................................32
Table 10. Dummy Cycle and Frequency Table (MHz)................................................................................32
9-10. Write Status Register (WRSR).................................................................................................................. 33
Table 11. Protection Modes........................................................................................................................34
9-11. Read Data Bytes (READ)......................................................................................................................... 36
9-12. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 37
9-13. Dual Output Read Mode (DREAD)........................................................................................................... 38
9-14. 2 x I/O Read Mode (2READ).................................................................................................................... 39
9-15. Quad Read Mode (QREAD)..................................................................................................................... 40
9-16. 4 x I/O Read Mode (4READ).................................................................................................................... 41
9-17. Burst Read................................................................................................................................................ 43
9-18. Performance Enhance Mode - XIP (execute-in-place)............................................................................. 44
9-19. Sector Erase (SE)..................................................................................................................................... 47
9-20. Block Erase (BE32K)................................................................................................................................ 48
9-21. Block Erase (BE)...................................................................................................................................... 49
9-22. Chip Erase (CE)........................................................................................................................................ 50
9-23. Page Program (PP).................................................................................................................................. 51

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

2
 MX25L12872F

9-24.4 x I/O Page Program (4PP)..................................................................................................................... 53

[Link] Power-down (DP)............................................................................................................................ 54
[Link] Security Register (WRSCUR).......................................................................................................... 55
[Link] Security Register (RDSCUR).......................................................................................................... 56
[Link] Secured OTP (ENSO)..................................................................................................................... 57
[Link] Secured OTP (EXSO)........................................................................................................................ 57
Table 12. Security Register Definition........................................................................................................58
9-30. Write Protection Selection (WPSEL)......................................................................................................... 59
9-31. Advanced Sector Protection..................................................................................................................... 61
Table 13. Lock Register..............................................................................................................................62
Table 14. SPB Register..............................................................................................................................63
Table 15. DPB Register..............................................................................................................................65
9-32. Program/Erase Suspend/Resume............................................................................................................ 67
9-33. Erase Suspend......................................................................................................................................... 67
9-34. Program Suspend..................................................................................................................................... 67
9-35. Write-Resume........................................................................................................................................... 69
9-36. No Operation (NOP)................................................................................................................................. 69
9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 69
9-38. Read SFDP Mode (RDSFDP)................................................................................................................... 71
10. RESET.................................................................................................................................................................. 72
Table 16. Reset Timing-(Other Operation).................................................................................................72
11. POWER-ON STATE.............................................................................................................................................. 73
12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 74
Table 17. ABSOLUTE MAXIMUM RATINGS.............................................................................................74
Table 18. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................74
Table 19. DC CHARACTERISTICS ..........................................................................................................76
Table 20. AC CHARACTERISTICS ..........................................................................................................77
13. OPERATING CONDITIONS.................................................................................................................................. 79
Table 21. Power-Up/Down Voltage and Timing..........................................................................................81
13-1. INITIAL DELIVERY STATE....................................................................................................................... 81
14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 82
15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ................................................................... 82
16. DATA RETENTION............................................................................................................................................... 83
17. LATCH-UP CHARACTERISTICS......................................................................................................................... 83
18. ORDERING INFORMATION................................................................................................................................. 84
19. PART NAME DESCRIPTION................................................................................................................................ 85
20. PACKAGE INFORMATION................................................................................................................................... 86
20-1. 8-pins SOP (200mil).................................................................................................................................. 86
20-2. 8-land WSON (6x5mm)............................................................................................................................ 87
21. REVISION HISTORY ............................................................................................................................................ 88

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

3
 MX25L12872F
3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL • Command Reset
• Supports Serial Peripheral Interface -- Mode 0 and • Program/Erase Suspend and Resume operation
Mode 3 • Electronic Identification
• Single Power Supply Operation - JEDEC 1-byte manufacturer ID and 2-byte device
- 2.7 to 3.6 volts for read, erase, and program ID
operations - RES command for 1-byte Device ID
• 134,217,728 x 1 bit structure - REMS command for 1-byte manufacturer ID and
or 67,108,864 x 2 bits (two I/O mode) structure 1-byte device ID
or 33,554,432 x 4 bits (four I/O mode) structure • Supports Serial Flash Discoverable Parameters
• Protocol Support (SFDP) mode
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V HARDWARE FEATURES
• Fast read for SPI mode • SCLK Input
- Supports clock frequencies up to 133MHz for all - Serial clock input
protocols • SI/SIO0
- Supports Fast Read, 2READ, DREAD, 4READ, - Serial Data Input or Serial Data Input/Output for 2
QREAD instructions. x I/O read mode and 4 x I/O read mode
- Configurable dummy cycle number for fast read • SO/SIO1
operation - Serial Data Output or Serial Data Input/Output for
• Supports Performance Enhance Mode - XIP 2 x I/O read mode and 4 x I/O read mode
(execute-in-place) • SIO2
• Default Quad I/O enable (QE bit=1), and cannot be - Serial Data Input/Output for 4 x I/O read mode
changed • SIO3
• Quad Peripheral Interface (QPI) available - Serial Data Input/Output for 4 x I/O read mode
• Equal 4K byte sectors, or Equal Blocks with 32K • PACKAGE
bytes or 64K bytes each -8-pin SOP (200mil)
- Any Block can be erased individually -8-land WSON (6x5mm)
• Programming : - All devices are RoHS Compliant and Halogen-
- 256byte page buffer free
- Quad Input/Output page program(4PP) to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention

SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bit defines the size of
the area to be protection against program and erase
instructions
- Advanced sector protection function (Solid Protect)
• Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

4
 MX25L12872F

2. GENERAL DESCRIPTION

MX25L12872F is 128Mb bits Serial NOR Flash memory, which is configured as 16,777,216 x 8 internally. When it is
in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12872F features
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin, and
SIO2 pin and SIO3 pin are also enabled for address/dummy bits input and data output.

The MX25L12872F MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or
whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please refer to security features section
for more details.

When the device is not in operation and CS# is high, it will remain in standby mode.

The MX25L12872F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.

Table 1. Read performance Comparison

Dual Output Quad Output Dual IO Quad IO
Numbers of Fast Read
Fast Read Fast Read Fast Read Fast Read
Dummy Cycles (MHz)
(MHz) (MHz) (MHz) (MHz)
4 - - - 84* 66
6 104 104 84 104 84*
8 104* 104* 104* 104 104
10 133 133 133 133 120/133R

Notes:
1. * Default Status.
2. R means VCC range = 3.0V-3.6V.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

5
 MX25L12872F

3. PIN CONFIGURATIONS 4. PIN DESCRIPTION

8-PIN SOP (200mil) SYMBOL DESCRIPTION

CS# Chip Select
CS# 1 8 VCC Serial Data Input (for 1 x I/O)/ Serial
SO/SIO1 2 7 SIO3 SI/SIO0 Data Input & Output (for 2xI/O or 4xI/O
SIO2 3 6 SCLK read mode)
GND 4 5 SI/SIO0
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O
read mode)
SCLK Clock Input
8-WSON (6x5mm) Serial Data Input & Output (for 4xI/O
SIO2
read mode)
CS# 1 8 VCC Serial Data Input & Output (for 4xI/O
SIO3
SO/SIO1 2 7 SIO3 read mode)
SIO2 3 6 SCLK VCC + 3V Power Supply
GND 4 5 SI/SIO0 GND Ground

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

6
 MX25L12872F

5. BLOCK DIAGRAM

X-Decoder
Address Memory Array
Generator

SI/SIO0
Y-Decoder
SO/SIO1
SIO2 * Data
SIO3 * Register
WP# *
SRAM Sense
HOLD# * Buffer Amplifier
RESET# *
CS#
Mode State HV
Logic Machine Generator

SCLK Clock Generator

Output
Buffer

* Depends on part number options.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

7
 MX25L12872F

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other commands to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES), and softreset command.

• Advanced Security Features: there are some protection and security features which protect content from inad-
vertent write and hostile access.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

8
 MX25L12872F

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected ar-
eas are more flexible which may protect various area by setting value of BP0-BP3 bits.

Table 2. Protected Area Sizes

Protected Area Sizes (T/B bit = 0)
Status bit Protect Level
BP3 BP2 BP1 BP0 128Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 255th)
0 0 1 0 2 (2 blocks, block 254th-255th)
0 0 1 1 3 (4 blocks, block 252nd-255th)
0 1 0 0 4 (8 blocks, block 248th-255th)
0 1 0 1 5 (16 blocks, block 240th-255th)
0 1 1 0 6 (32 blocks, block 224th-255th)
0 1 1 1 7 (64 blocks, block 192nd-255th)
1 0 0 0 8 (128 blocks, block 128th-255th)
1 0 0 1 9 (256 blocks, protected all)
1 0 1 0 10 (256 blocks, protected all)
1 0 1 1 11 (256 blocks, protected all)
1 1 0 0 12 (256 blocks, protected all)
1 1 0 1 13 (256 blocks, protected all)
1 1 1 0 14 (256 blocks, protected all)
1 1 1 1 15 (256 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Status bit Protect Level
BP3 BP2 BP1 BP0 128Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 0th)
0 0 1 0 2 (2 blocks, protected block 0th-1st)
0 0 1 1 3 (4 blocks, protected block 0th-3rd)
0 1 0 0 4 (8 blocks, protected block 0th-7th)
0 1 0 1 5 (16 blocks, protected block 0th-15th)
0 1 1 0 6 (32 blocks, protected block 0th-31st)
0 1 1 1 7 (64 blocks, protected block 0th-63rd)
1 0 0 0 8 (128 blocks, protected block 0th-127th)
1 0 0 1 9 (256 blocks, protected all)
1 0 1 0 10 (256 blocks, protected all)
1 0 1 1 11 (256 blocks, protected all)
1 1 0 0 12 (256 blocks, protected all)
1 1 0 1 13 (256 blocks, protected all)
1 1 1 0 14 (256 blocks, protected all)
1 1 1 1 15 (256 blocks, protected all)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

9
 MX25L12872F

II. Additional 8K-bit secured OTP for an unique identifier to provide an 8K-bit one-time program area for setting a
device unique serial number. This may be accomplished in the factory or by an end systems customer.

The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP area
and factory could lock the other.

- Security register bit 0 indicates whether the second 4K-bit is locked by factory or not.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-
mand to set customer lock-down bit1 as "1". Please refer to "Table 12. Security Register Definition" for security reg-
ister bit definition and "Table 3. 8K-bit Secured OTP Definition" for address range definition.

- The 8K-bit secured OTP area is programmed by entering secured OTP mode (with the Enter Security OTP
command), and going through a normal program procedure. Exiting secured OTP mode is done by issuing the
Exit Security OTP command.

Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any
more. While in 8K-bit Secured OTP mode, array access is not allowed.

Table 3. 8K-bit Secured OTP Definition

Address range Size Customer Lock Standard Factory Lock
xxx000-xxx1FF 4096-bit Determined by customer N/A
xxx200-xxx3FF 4096-bit N/A Determined by factory

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

10
 MX25L12872F

7. Memory Organization

Table 4. Memory Organization

Block(64K-byte) Block(32K-byte) Sector Address Range

4095 FFF000h FFFFFFh

…
511
4088 FF8000h FF8FFFh individual 16 sectors
255
lock/unlock unit:4K-byte
4087 FF7000h FF7FFFh
510

…
4080 FF0000h FF0FFFh
4079 FEF000h FEFFFFh
509

…
4072 FE8000h FE8FFFh
254
4071 FE7000h FE7FFFh
508

…
individual block 4064 FE0000h FE0FFFh
lock/unlock unit:64K-byte
4063 FDF000h FDFFFFh
507
…

4056 FD8000h FD8FFFh

253
4055 FD7000h FD7FFFh
506
…

4048 FD0000h FD0FFFh

individual block
lock/unlock unit:64K-byte

47 02F000h 02FFFFh
5
…

2 40 028000h 028FFFh
39 027000h 027FFFh
4
…

individual block 32 020000h 020FFFh

lock/unlock unit:64K-byte
31 01F000h 01FFFFh
3
…

24 018000h 018FFFh
1
23 017000h 017FFFh
2
…

16 010000h 010FFFh
15 00F000h 00FFFFh
1
…

8 008000h 008FFFh individual 16 sectors

0 7 007000h 007FFFh lock/unlock unit:4K-byte
0
…

0 000000h 000FFFh

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

11
 MX25L12872F

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.

2. When an incorrect command is written to this device, it enters standby mode and stays in standby mode until the
next CS# falling edge. In standby mode, This device's SO pin should be High-Z.

3. When a correct command is written to this device, it enters active mode and stays in active mode until the next
CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,
RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDLR, RDCR the shifted-in instruction sequence is followed by
a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions:
WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, GBLK, GBULK,
SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.

6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is ig-
nored and will not affect the current operation of Write Status Register, Program, or Erase.

Figure 1. Serial Modes Supported

CPOL CPHA shift in shift out

(Serial mode 0) 0 0 SCLK

(Serial mode 3) 1 1 SCLK

SI MSB

SO MSB

Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

12
 MX25L12872F

Figure 2. Serial Input Timing

tSHSL

CS#

tCHSL tSLCH tCHSH tSHCH

SCLK

tDVCH tCHCL

tCHDX tCLCH

SI MSB LSB

High-Z
SO

Figure 3. Output Timing

CS#
tCH

SCLK
tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX

SO LSB

SI [Link] IN

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

13
 MX25L12872F

8-1. Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface
in command cycles, address cycles and as well as data output cycles.

Enable QPI mode

By issuing EQIO command (35h), the QPI mode is enabled. After QPI mode has been enabled, the device enter
quad mode (4-4-4) without QE bit status changed.

Figure 4. Enable QPI Sequence

CS#

MODE 3 0 1 2 3 4 5 6 7

SCLK MODE 0

SIO0 35h

SIO[3:1]

Reset QPI (RSTQIO)

To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).

Note:
For EQIO and RSTQIO commands, CS# high width has to follow "From Write/Erase/Program to Read Status
Register spec" tSHSL (as defined in "Table 20. AC CHARACTERISTICS") for next instruction.

Figure 5. Reset QPI Mode

CS#

SCLK

SIO[3:0] F5h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

14
 MX25L12872F

9. COMMAND DESCRIPTION
Table 5. Command Set

Address Byte
Command Total Dummy Data
SPI QPI
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
Array access
READ
03 (hex) V 3 ADD1 ADD2 ADD3 0 1- ∞
(normal read)
FAST READ
0B (hex) V 3 ADD1 ADD2 ADD3 8* 1- ∞
(fast read data)
2READ
BB (hex) V 3 ADD1 ADD2 ADD3 4* 1- ∞
(2 x I/O read command)
DREAD
3B (hex) V 3 ADD1 ADD2 ADD3 8* 1- ∞
(1I 2O read)
4READ
EB (hex) V V 3 ADD1 ADD2 ADD3 6 * 1- ∞
(4 I/O read)
QREAD
6B (hex) V 3 ADD1 ADD2 ADD3 8* 1- ∞
(1I 4O read)
PP
02 (hex) V V 3 ADD1 ADD2 ADD3 0 1-256
(page program)
4PP
38 (hex) V 3 ADD1 ADD2 ADD3 0 1-256
(quad page program)
SE
20 (hex) V V 3 ADD1 ADD2 ADD3 0 0
(sector erase)
BE 32K
52 (hex) V V 3 ADD1 ADD2 ADD3 0 0
(block erase 32KB)
BE
D8 (hex) V V 3 ADD1 ADD2 ADD3 0 0
(block erase 64KB)
CE 60 or C7
V V 0 0 0
(chip erase) (hex)
Device operation
WREN
06 (hex) V V 0 0 0
(write enable)
WRDI
04 (hex) V V 0 0 0
(write disable)
WPSEL
68 (hex) V V 0 0 0
(Write Protect Selection)
EQIO
35 (hex) V 0 0 0
(Enable QPI)
RSTQIO
F5 (hex) V 0 0 0
(Reset QPI)
PGM/ERS Suspend 75 or B0
V V 0 0 0
(Suspends Program/ Erase) (hex)
PGM/ERS Resume 7A or 30
V V 0 0 0
(Resumes Program/ Erase) (hex)
DP
B9 (hex) V V 0 0 0
(Deep power down)
RDP
(Release from deep power AB (hex) V V 0 0 0
down)

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

15
 MX25L12872F

Address Byte
Command Total Dummy Data
SPI QPI
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
NOP
00 (hex) V V 0 0 0
(No Operation)
RSTEN 66 (hex) V V 0 0 0
(Reset Enable) (Note2)
RST 99 (hex) V V 0 0 0
(Reset Memory) (Note2)
GBLK
7E (hex) V V 0 0 0
(gang block lock)
GBULK
98 (hex) V V 0 0 0
(gang block unlock)
FMEN
41 (hex) V V 0 0 0
(factory mode enable)
Register Access
RDID
9F (hex) V 0 0 3
(read identification)
RES
AB (hex) V V 0 24 1
(read electronic ID)
REMS
(read electronic manufacturer 90 (hex) V 0 ADD1 16 2
& device ID)
QPIID
AF (hex) V 0 0 3
(QPI ID Read)
RDSFDP
5A (hex) V 3 ADD1 ADD2 ADD3 8 1- ∞
(Read SFDP Table)
RDSR
05 (hex) V V 0 0 1
(read status register)
RDCR
15 (hex) V V 0 0 1
(read configuration register)
WRSR
(write status/configuration 01 (hex) V V 0 0 1-2
register)
RDSCUR
2B (hex) V V 0 0 1
(read security register)
WRSCUR
2F (hex) V V 0 0 0
(write security register)
SBL
C0 (hex) V V 0 0 1
(Set Burst Length)
ENSO
B1 (hex) V V 0 0 0
(enter secured OTP)
EXSO
C1 (hex) V V 0 0 0
(exit secured OTP)
WRLR
2C (hex) V 0 0 2
(write Lock register)
RDLR
2D (hex) V 0 0 2
(read Lock register)
WRSPB
E3 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 0
(SPB bit program)
ESSPB
E4 (hex) V 0 0 0
(all SPB bit erase)
RDSPB
E2 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1
(read SPB status)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

16
 MX25L12872F

Address Byte
Command Total Dummy Data
SPI QPI
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
WRDPB
E1 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1
(write DPB register)
RDDPB
E0 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1
(read DPB register)
Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

17
 MX25L12872F

9-1. Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Instructions like PP, 4PP, SE, BE32K,
BE, CE, and WRSR that are intended to change the device content, should be preceded by the WREN instruction.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care in SPI mode.

Figure 6. Write Enable (WREN) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command

SI 06h

High-Z
SO

Figure 7. Write Enable (WREN) Sequence (QPI Mode)

CS#

Mode 3 0 1
SCLK
Mode 0 Command

SIO[3:0] 06h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

18
 MX25L12872F

9-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care in SPI mode.

The WEL bit is reset in the following situations:

- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- GBLK command completion
- GBULK command completion
- WRLR command completion
- WRSPB command completion
- ESSPB command completion
- WRDPB command completion

Figure 8. Write Disable (WRDI) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK

Mode 0
Command

SI 04h

High-Z
SO

Figure 9. Write Disable (WRDI) Sequence (QPI Mode)

CS#
Mode 3 0 1
SCLK
Mode 0 Command

SIO[3:0] 04h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

19
 MX25L12872F

9-3. Factory Mode Enable (FMEN)

The Factory Mode Enable (FMEN) instruction enhances Program and Erase performance to increase factory pro-
duction throughput. The FMEN instruction needs to be combined with the instructions which are intended to change
the device content, like PP, 4PP, SE, BE32K, BE, and CE.

The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes high. A valid
factory mode operation need to included three sequences: WREN instruction → FMEN instruction→ Program or
Erase instruction.

Suspend command is not acceptable under factory mode.

The FMEN is reset in the following situations

- Power-up
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- Softreset command completion

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care in SPI mode.

Figure 10. Factory Mode Enable (FMEN) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command

SI 41h

High-Z
SO

Figure 11. Factory Mode Enable (FMEN) Sequence (QPI Mode)

CS#

Mode 3 0 1
SCLK
Mode 0 Command

SIO[3:0] 41h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

20
 MX25L12872F

9-4. Read Identification (RDID)

The RDID instruction is for reading the 1-byte manufacturer ID and the 2-byte Device ID that follows. The Macronix
Manufacturer ID and Device ID are listed as "Table 6. ID Definitions".

The sequence of issuing RDID instruction is: CS# goes low→ send RDID instruction code→24-bits ID data out on
SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.

Figure 12. Read Identification (RDID) Sequence (SPI mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31
SCLK

Mode 0
Command

SI 9Fh

Manufacturer Identification Device Identification

High-Z
SO 7 6 5 2 1 0 15 14 13 3 2 1 0

MSB MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

21
 MX25L12872F

9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Se-
lect (CS#) must remain High for at least tRES1(max), as specified in "Table 20. AC CHARACTERISTICS". Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID
Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.

The RDP and RES are allowed to execute in Deep power-down mode, except if the device is in progress of pro-
gram/erase/write cycle; In this case, there is no effect on the current program/erase/write cycle that is in progress.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The RES instruction ends when CS# goes high, after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.

Figure 13. Read Electronic Signature (RES) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command 3 Dummy Bytes tRES2

SI ABh 23 22 21 3 2 1 0

MSB
Electronic Signature ID
High-Z
SO 7 6 5 4 3 2 1 0
MSB

Deep Power-down Mode Stand-by Mode

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

22
 MX25L12872F

Figure 14. Read Electronic Signature (RES) Sequence (QPI Mode)

CS#
MODE 3 0 1 2 3 4 5 6 7
SCLK
MODE 0 tRES2
Command 3 Dummy Bytes

SIO[3:0] ABh X X X X X X H0 L0
MSB LSB
Data In Electronic
Signature ID

Deep Power-down Mode Stand-by Mode

Figure 15. Release from Deep Power-down (RDP) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 tRES1

SCLK

Mode 0 Command

SI ABh

High-Z
SO

Deep Power-down Mode Stand-by Mode

Figure 16. Release from Deep Power-down (RDP) Sequence (QPI Mode)

CS#
tRES1
Mode 3 0 1
SCLK
Mode 0

Command

SIO[3:0] ABh

Deep Power-down Mode Stand-by Mode

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

23
 MX25L12872F

9-6. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in "Table 6. ID Definitions".

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the
manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be
output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read con-
tinuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 17. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10
SCLK

Mode 0
Command 2 Dummy Bytes

SI 15 14 13 3 2 1 0
90h

High-Z
SO

CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK

ADD (1)

SI 7 6 5 4 3 2 1 0

Manufacturer ID Device ID

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

Note: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

24
 MX25L12872F

9-7. QPI ID Read (QPIID)

The QPIID Read instruction can be used to identify the Device ID and Manufacturer ID. The sequence of issuing
the QPIID instruction is as follows: CS# goes low→send QPI ID instruction→Data out on SO→CS# goes high. Most
significant bit (MSB) first.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The Manufacturer ID,
Memory Type, and Memory Density data byte will be output continuously, until the CS# goes high.

Table 6. ID Definitions

Command Type MX25L12872F

Manufacturer ID Memory Type Memory Density
RDID 9Fh
C2 20 18
Electronic ID
RES ABh
17
Manufacturer ID Device ID
REMS 90h
C2 17
Manufacturer ID Memory Type Memory Density
QPIID AFh
C2 20 18

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

25
 MX25L12872F

9-8. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ send RDSR instruction code→ Status Register data
out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

Figure 18. Read Status Register (RDSR) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Mode 0
command

SI 05h

Status Register Out Status Register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 19. Read Status Register (RDSR) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7 N
SCLK
Mode 0

SIO[3:0] 05h H0 L0 H0 L0 H0 L0 H0 L0
MSB LSB
Status Byte Status Byte Status Byte Status Byte

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

26
 MX25L12872F

9-9. Read Configuration Register (RDCR)

The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ send RDCR instruction code→ Configuration Register
data out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

Figure 20. Read Configuration Register (RDCR) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Mode 0
command

SI 15h

Configuration register Out Configuration register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 21. Read Configuration Register (RDCR) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7 N
SCLK
Mode 0

SIO[3:0] 15h H0 L0 H0 L0 H0 L0 H0 L0
MSB LSB
Config. Byte Config. Byte Config. Byte Config. Byte

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

27
 MX25L12872F

For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:

Figure 22. Program/Erase flow with read array data

start

WREN command

RDSR command*

No
WEL=1?

Yes
Program/erase command

Write program data/address

(Write erase address)

RDSR command

No
WIP=0?

Yes
RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Read array data

(same address of PGM/ERS)

No
Verify OK?

Yes
Program/erase successfully Program/erase fail

Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
No
Program/erase completed

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

28
 MX25L12872F

Figure 23. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)

start

WREN command

RDSR command*

No
WEL=1?

Yes
Program/erase command

Write program data/address

(Write erase address)

RDSR command

No
WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

RDSCUR command

Yes
P_FAIL/E_FAIL =1 ?

No
Program/erase successfully Program/erase fail

Program/erase Yes
another block?
* Issue RDSR to check BP[3:0].
No * If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Program/erase completed

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

29
 MX25L12872F

Status Register

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta-
tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register
progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register
cycle.

WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)
instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-
protected.

QE bit. The Quad Enable (QE) bit is permanently set to "1". When QE is "1", Quad mode is enabled and Quad
mode commands are supported along with Single and Dual mode commands.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0".

Table 7. Status Register

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BP3 BP2 BP1 BP0
SRWD (status QE WEL WIP
(level of (level of (level of (level of
register write (Quad (write enable (write in
protected protected protected protected
protect) Enable) latch) progress bit)
block) block) block) block)
1=status
register write 1=write 1=write
1=Quad
disable enable operation
Enabled (note 1) (note 1) (note 1) (note 1)
0=status 0=not write 0=not in write
register write enable operation
enable
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
volatile bit volatile bit
bit bit bit bit bit bit
Note 1: Please refer to the "Table 2. Protected Area Sizes".

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

30
 MX25L12872F

Configuration Register

The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.

ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in "Table 9. Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30 Ohms
when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be
executed.

TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

Table 8. Configuration Register Table

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

DC1 DC0 TB ODS 2 ODS 1 ODS 0
(Dummy (Dummy Reserved Reserved (top/bottom (output driver (output driver (output driver
cycle 1) cycle 0) selected) strength) strength) strength)
0=Top area
protect
(note 2) (note 2) x x 1=Bottom (note 1) (note 1) (note 1)
area protect
(Default=0)
volatile bit volatile bit x x OTP volatile bit volatile bit volatile bit

Note 1: Please refer to "Table 9. Output Driver Strength Table"

Note 2: Please refer to "Table 10. Dummy Cycle and Frequency Table (MHz)"

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

31
 MX25L12872F

Table 9. Output Driver Strength Table

Output Driver Strength
ODS2 ODS1 ODS0
Resistance (Ohm) %
0 0 0 Reserved -
0 0 1 90 Ohms 25%
0 1 0 45 Ohms 45%
0 1 1 45 Ohms 45%
1 0 0 Reserved -
1 0 1 15 Ohms 100%
1 1 0 15 Ohms 100%
1 1 1 30 Ohms (Default) 75% (Default)

Table 10. Dummy Cycle and Frequency Table (MHz)

Numbers of Dummy Dual Output Fast Quad Output Fast
DC[1:0] Fast Read
clock cycles Read Read
00 (default) 8 104 104 104
01 6 104 104 84
10 8 104 104 104
11 10 133 133 133

Numbers of Dummy
DC[1:0] Dual IO Fast Read
clock cycles
00 (default) 4 84
01 6 104
10 8 104
11 10 133

Numbers of Dummy
DC[1:0] Quad IO Fast Read
clock cycles
00 (default) 6 84
01 4 66
10 8 104
11 10 120/133R

Note: "R" mean VCC range= 3.0V-3.6V.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

32
 MX25L12872F

9-10. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes").

The sequence of issuing WRSR instruction is: CS# goes low→ send WRSR instruction code→ Status Register data
on SI→Configuration Register data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-
able Latch (WEL) bit is reset.

Figure 24. Write Status Register (WRSR) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
command Status Configuration
Register In Register In

SI 01h 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

High-Z MSB
SO

Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 25. Write Status Register (WRSR) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 Mode 3

SCLK
Mode 0 Mode 0

Command SR in CR in

SIO[3:0] 01h H0 L0 H1 L1

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

33
 MX25L12872F

Software Protected Mode (SPM):

- When SRWD bit is defaulted as 0, the WREN instruction may set the WEL bit and can change the values of
BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software
protected mode (SPM).

Table 11. Protection Modes

Mode Status register condition SRWD bit status Memory

Software protection Status register can be written

The protected area cannot
mode (SPM) in (WEL bit is set to "1") and SRWD bit=0
be programmed or erased.
BP0-BP3 bits can be changed

Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2.
Protected Area Sizes".

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

34
 MX25L12872F

Figure 26. WRSR flow

start

WREN command

RDSR command

No
WEL=1?

Yes
WRSR command

Write status register data

RDSR command

No
WIP=0?

Yes
RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No
Verify OK?

Yes
WRSR successfully WRSR fail

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

35
 MX25L12872F

9-11. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, READ instruction is rejected without any impact on
the Program/Erase/Write Status Register current cycle.

Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCLK
Mode 0
command 24-Bit Address

SI 03h 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High-Z
SO 7 6 5 4 3 2 1 0 7
MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

36
 MX25L12872F

9-12. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low→ send FAST_READ instruction code→ 3-byte
address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_READ operation can use CS# to high
at any time during data out.

In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.

Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Mode 0
Command 24-Bit Address

SI 0Bh 23 22 21 3 2 1 0

High-Z
SO

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Configurable
Dummy Cycle

SI 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

Notes: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

37
 MX25L12872F

9-13. Dual Output Read Mode (DREAD)

The DREAD instruction enables double throughput of the Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK
at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing
DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low→ send DREAD instruction→3-byte address on
SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation, raise
CS# high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

Figure 29. Dual Read Mode Sequence (SPI Mode only)

CS#

0 1 2 3 4 5 6 7 8 9 30 31 32 39 40 41 42 43 44 45
SCLK
… …
Command 24 ADD Cycle Configurable Data Out Data Out
Dummy Cycle 1 2

SI/SIO0 3B A23 A22 … A1 A0 D6 D4 D2 D0 D6 D4

High Impedance
SO/SIO1 D7 D5 D3 D1 D7 D5

Notes: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

38
 MX25L12872F

9-14. 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on ris-
ing edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte address inter-
leave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3
SCLK
Mode 0 Mode 0
12 ADD Cycles Configurable Data Data
Command
Dummy Cycle Out 1 Out 2

SI/SIO0 BBh A22 A20 A18 A4 A2 A D6 D4 D2 D0 D6 D4 D2 D0

SO/SIO1 A23 A21 A19 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1

Notes: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

39
 MX25L12872F

9-15. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. The address is latched on ris-
ing edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on
SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

Figure 31. Quad Read Mode Sequence (SPI Mode only)

CS#

0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 38 39 40 41 42
SCLK
… …
Command 24 ADD Cycles Configurable Data Data Data
dummy cycles Out 1 Out 2 Out 3

SIO0 6B A23 A22 … A2 A1 A0 D4 D0 D4 D0 D4

High Impedance
SIO1 D5 D1 D5 D1 D5

High Impedance
SIO2 D6 D2 D6 D2 D6

High Impedance
SIO3 D7 D3 D7 D3 D7

Notes: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

40
 MX25L12872F

9-16. 4 x I/O Read Mode (4READ)

The 4READ instruction enables quad throughput of the Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ send 4READ
instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out inter-
leave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out.

4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low→ send 4READ instruction→ 3-byte address interleave on
SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end
4READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

41
 MX25L12872F

Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mode 3
SCLK
Mode 0 Mode 0
Command 6 ADD Cycles Data Data Data
Performance Out 1 Out 2 Out 3
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 3)

SIO0 EBh A20 A16 A12 A8 A4 A P4 P0 D4 D0 D4 D0 D4 D0

SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1

SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2

SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3

Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)

CS#

MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3
SCLK
MODE 0 MODE 0

SIO[3:0] EBh A5 A4 A3 A2 A1 A0 X X X X H0 L0 H1 L1 H2 L2 H3 L3
P(7:4) P(3:0)
Performance
24-bit Address MSB
Data In enhance
indicator (Note 1) Data Out

Configurable Dummy Cycles

(Note 3)

Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

42
 MX25L12872F

9-17. Burst Read

The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple read
commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst
Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the
initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned
boundary containing the initial read address.

To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code (C0h) → send WRAP CODE
→drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.
Data Wrap Around Wrap Depth
00h Yes 8-byte
01h Yes 16-byte
02h Yes 32-byte
03h Yes 64-byte
1xh No X

Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode
4READ read commands support the wrap around feature after Burst Read is enabled. To change the wrap depth,
resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read
instruction with Wrap Code 1xh. QPI and SPI “EBh” support wrap around feature after wrap around is enabled. Both
SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't care
during SPI mode.

Figure 34. Burst Read - SPI Mode

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 1 12 13 14 15

SCLK
Mode 0

SI C0h D7 D6 D5 D4 D3 D2 D1 D0

Figure 35. Burst Read - QPI Mode

CS#

Mode 3 0 1 2 3

SCLK
Mode 0

SIO[3:0] C0h H0 L0

MSB LSB

Note: MSB=Most Significant Bit

LSB=Least Significant Bit

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

43
 MX25L12872F

9-18. Performance Enhance Mode - XIP (execute-in-place)

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

Performance enhance mode is supported in both SPI and QPI mode.

In QPI mode, “EBh” and SPI “EBh” commands support enhance mode. The performance enhance mode is not
supported in dual I/O mode.

To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.

This sequence of issuing 4READ instruction is especially useful in random access: CS# goes low→send 4READ
instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→
4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (The following 4READ instruction is not
allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 3-bytes random access
address.

To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be is-
sued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.

If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

44
 MX25L12872F

Figure 36. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n
SCLK
Mode 0
Command 6 ADD Cycles Data Data Data
Performance Out 1 Out 2 Out n
enhance
indicator (Note 1)

Configurable
Dummy Cycle (Note 2)

SIO0 EBh A20 A16 A12 A8 A4 A P4 P0 D4 D0 D4 D0 D4 D0

SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1

SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2

SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3

CS#

n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3

SCLK
Mode 0
6 ADD Cycles Data Data Data
Performance Out 1 Out 2 Out n
enhance
indicator (Note 1)

Configurable
Dummy Cycle (Note 2)

SIO0 A20 A16 A12 A8 A4 A P4 P0 D4 D0 D4 D0 D4 D0

SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1

SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2

SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3

Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

45
 MX25L12872F

Figure 37. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCLK
Mode 0
SIO[3:0] EBh A5 A4 A3 A2 A1 A0 X X X X H0 L0 H1 L1
MSB LSB MSB LSB
P(7:4) P(3:0)
Data In
Data Out
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)

CS#
n+1 .............

SCLK
Mode 0
SIO[3:0] A5 A4 A3 A2 A1 A0 X X X X H0 L0 H1 L1
P(7:4) P(3:0) MSB LSB MSB LSB

6 Address cycles Data Out

performance
enhance
indicator

Configurable
Dummy Cycle (Note 1)

Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

46
 MX25L12872F

9-19. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (please refer to "Table 4. Memory Organization") is a valid
address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant
bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low→ send SE instruction code→ 3-byte address on SI→ CS#
goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode), the Sector Erase (SE) instruction will not be executed on the block.

Figure 38. Sector Erase (SE) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Mode 0
Command 24-Bit Address

SI 20h A23 A22 A2 A1 A0

MSB

Figure 39. Sector Erase (SE) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
24-Bit Address
Command

SIO[3:0] 20h A5 A4 A3 A2 A1 A0
MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

47
 MX25L12872F

9-20. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 4. Memory Organiza-
tion") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE32K instruction is: CS# goes low→ send BE32K instruction code→ 3-byte address on
SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode), the Block Erase (BE32K) instruction will not be executed on the block.

Figure 40. Block Erase 32KB (BE32K) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Mode 0
Command 24-Bit Address

SI 52h A23 A22 A2 A1 A0

MSB

Figure 41. Block Erase 32KB (BE32K) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command 24-Bit Address

SIO[3:0] 52h A5 A4 A3 A2 A1 A0
MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

48
 MX25L12872F

9-21. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organiza-
tion") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low→ send BE instruction code→ 3-byte address on SI→ CS#
goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protection mode), the Block Erase (BE) instruction will not be executed on the block.

Figure 42. Block Erase (BE) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Mode 0
Command 24-Bit Address

SI D8h A23 A22 A2 A1 A0

MSB

Figure 43. Block Erase (BE) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command 24-Bit Address

SIO[3:0] D8h A5 A4 A3 A2 A1 A0
MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

49
 MX25L12872F

9-22. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→send CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-
ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block Lock (BP) protection mode" (WPSEL=0): The Chip Erase(CE) instruction will not be
executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

When the chip is under "Advanced Sector Protection mode" (WPSEL=1): The Chip Erase (CE) instruction will be
executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected
in top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 44. Chip Erase (CE) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command

SI 60h or C7h

Figure 45. Chip Erase (CE) Sequence (QPI Mode)

CS#
Mode 3 0 1
SCLK
Mode 0 Command

SIO[3:0] 60h or C7h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

50
 MX25L12872F

9-23. Page Program (PP)

The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the de-
vice to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires
that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies the starting
address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected
page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be pro-
grammed, A[7:0] should be set to 0.

The sequence of issuing PP instruction is: CS# goes low→ send PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (
the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode) the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

51
 MX25L12872F

Figure 46. Page Program (PP) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
Command 24-Bit Address Data Byte 1

SI 02h 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

CS#

2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

Figure 47. Page Program (PP) Sequence (QPI Mode)

CS#

Mode 3 0 1 2
SCLK
Mode 0
Command 24-Bit Address

SIO[3:0] 02h A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 H255 L255

Data Byte Data Byte Data Byte Data Byte Data Byte
Data In
1 2 3 4 256

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

52
 MX25L12872F

9-24. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must be executed to set the Write Enable Latch (WEL) bit before sending the Quad Page Program (4PP).
The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can
improve programmer performance and the effectiveness of application. The other function descriptions are as same
as standard page program.

The sequence of issuing 4PP instruction is: CS# goes low→ send 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Ad-
vanced Sector Protection mode), the Quad Page Program (4PP) instruction will not be executed.

Figure 48. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Mode 0
Command 6 Address cycle Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4

SIO0 38h A20 A16 A12 A8 A4 A0 4 0 4 0 4 0 4 0

SIO1 A21 A17 A13 A9 A5 A1 5 1 5 1 5 1 5 1

SIO2 A22 A18 A14 A10 A6 A2 6 2 6 2 6 2 6 2

SIO3 A23 A19 A15 A11 A7 A3 7 3 7 3 7 3 7 3

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

53
 MX25L12872F

9-25. Deep Power-down (DP)

The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power-
down mode, in which the quiescent current is reduced from ISB1 to ISB2.

The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must
go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the
instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this in-
struction. SIO[3:1] are "don't care".

After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down
mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be
ignored except Release from Deep Power-down (RDP).

The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep Pow-
erdown (RDP) instruction, power-cycle, or reset. Please refer to "Figure 15. Release from Deep Power-down (RDP) Se-
quence (SPI Mode)" and "Figure 16. Release from Deep Power-down (RDP) Sequence (QPI Mode)".

Figure 49. Deep Power-down (DP) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 tDP
Mode 3
SCLK
Mode 0
Command

SI B9h

Stand-by Mode Deep Power-down Mode

Figure 50. Deep Power-down (DP) Sequence (QPI Mode)

CS#
tDP
Mode 3 0 1
SCLK
Mode 0
Command

SIO[3:0] B9h

Stand-by Mode Deep Power-down Mode

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

54
 MX25L12872F

9-26. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ send WRSCUR instruction → CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

Figure 51. Write Security Register (WRSCUR) Sequence (SPI Mode)

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command

SI 2Fh

High-Z
SO

Figure 52. Write Security Register (WRSCUR) Sequence (QPI Mode)

CS#
Mode 3 0 1
SCLK
Mode 0 Command

SIO[3:0] 2Fh

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

55
 MX25L12872F

9-27. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→send RDSCUR instruction→Security Register
data out on SO→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

Figure 53. Read Security Register (RDSCUR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 2Bh

Security register Out Security register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 54. Read Security Register (RDSCUR) Sequence (QPI Mode)

CS#
Mode 3 0 1 2 3 4 5 6 7 N
SCLK
Mode 0

SIO[3:0] 2Bh H0 L0 H0 L0 H0 L0 H0 L0
MSB LSB
Security Byte Security Byte Security Byte Security Byte

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

56
 MX25L12872F

9-28. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 8K-bit secured OTP mode. The additional 8K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ send ENSO instruction to enter Secured OTP
mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or pro-
gram procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

9-29. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ send EXSO instruction to exit Secured OTP mode→
CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

57
 MX25L12872F

Security Register

The definition of the Security Register bits is as below:

Write Protection Selection bit. Please reference to "9-30. Write Protection Selection (WPSEL)".

Erase Fail bit. The Erase Fail bit indicates the status of last Erase operation. The bit will be set to "1" if the erase
operation failed or the erase region is protected. It will be automatically cleared to "0" if the next erase operation
succeeds. Please note that it does not interrupt or stop any operation in the flash memory.

Program Fail bit. The Program Fail bit indicates the status of last Program operation. The bit will be set to "1" if
the program operation failed or the program region is protected. It will be automatically cleared to "0" if the next
program operation succeeds. Please note that it does not interrupt or stop any operation in the flash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus­
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit Secured
OTP area cannot be updated any more. While it is in 8K-bit secured OTP mode, main array access is not allowed.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the 2nd 4K-bit Secured OTP area is locked by
factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Table 12. Security Register Definition

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LDSO Secured OTP
ESB PSB (lock-down Indicator bit
WPSEL E_FAIL P_FAIL Reserved (Erase (Program 1st 4K-bit (2nd 4K-bit
Suspend bit) Suspend bit) Secured Secured
OTP) OTP)

0= normal 0= not
0= Block Lock 0= normal 0= Erase 0= Program
Program lockdown
(BP) protection Erase is not is not 0= nonfactory
succeed 1= lock-down
mode succeed suspended suspended lock
1= indicate - (Secured
1= Advanced 1= indicate 1= Erase 1= Program 1= factory
Program OTP can no
Sector Protection Erase failed suspended suspended lock
failed longer be
(default=0) (default=0) (default=0) (default=0)
(default=0) programmed)

Non-volatile bit Non-volatile Non-volatile

Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit
(OTP) bit (OTP) bit (OTP)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

58
 MX25L12872F

9-30. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Individual Sector Protection mode is disa-
bled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL command
is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL com-
mand. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”.

When WPSEL = 0: Block Lock (BP) protection mode,

The memory array is write protected by the BP3-BP0 bits.

When WPSEL =1: Advanced Sector Protection mode,

Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the Dy-
namic Protection Bits (DPB) by default. The Individual Sector Protection instructions WRLR, RDLR, WRSPB, ES-
SPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3-BP0 bits of the Status Register are disabled
and have no effect.

The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Individual
Sector Protect mode → CS# goes high.

Figure 55. Write Protection Selection

Start
(Default in BP Mode)

WPSEL=1 Set WPSEL=0

WPSEL Bit

Advanced Block Protection

Sector Protection (BP)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

59
 MX25L12872F

Figure 56. WPSEL Flow

start

WREN command

RDSCUR command

Yes
WPSEL=1?

No
WPSEL disable,
block protected by BP[3:0]

WPSEL command

RDSR command

No
WIP=0?

Yes
RDSCUR command

No
WPSEL=1?

Yes
WPSEL set successfully WPSEL set fail

WPSEL enable.
Block protected by Advance Sector Protection

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

60
 MX25L12872F

9-31. Advanced Sector Protection

Advanced Sector Protection can protect individual 4KB sectors in the bottom and top 64KB of memory and protect
individual 64KB blocks in the rest of memory.

There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB) assigned to each
4KB sector at the bottom and top 64KB of memory and to each 64KB block in the rest of memory. A sector or block
is write-protected from programming or erasing when its associated SPB or DPB is set to “1”.

The figure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:

Solid Protection mode permits the SPB bits to be modified after power-on or a reset. The figure below is an
overview of Advanced Sector Protection.

Figure 57. Advanced Sector Protection Overview

Start

Set SPBLKDN# = 0 SPB Lock bit locked

SPB Lock Bit ? All SPB can not be changeable

SPBLKDN# = 1

SPB Lock bit Unlocked

SPB is changeable

Dynamic Protect Bit Register SPB Access Register

(DPB) (SPB)

Sector Array
DPB=1 sector protect SPB=1 Write Protect

DPB=0 sector unprotect SPB=0 Write Unprotect

DPB 0 SA 0 SPB 0

DPB 1 SA 1 SPB 1

DPB 2 SA 2 SPB 2
: : :
: : :

DPB N-1 SA N-1 SPB N-1

DPB N SA N SPB N

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

61
 MX25L12872F

9-31-1. Lock Register

The Lock Register is a 16-bit one-time programmable register. Lock Register bit [6] is SPB Lock Down Bit (SPBLKDN)
which is an unique bit assigned to control all SPB bit status.

When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed anymore, and
SPBLKDN bit itself can not be altered anymore, either.

The Lock Register is programmed using the WRLR (Write Lock Register) command. A WREN command must be
executed to set the WEL bit before sending the WRLR command.

Table 13. Lock Register

Default
Bits Field Name Function Type Description
State
15 to 7 RFU Reserved OTP 1 Reserved for Future Use
1 = SPB changeable
6 SPBLKDN SPB Lock Down OTP 1
0 = freeze SPB
5 to 0 RFU Reserved OTP 1 Reserved for Future Use

Figure 58. Read Lock Register (RDLR) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Mode 0
command

SI 2Dh

Register Out Register Out

High-Z
SO 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7

MSB MSB

Figure 59. Write Lock Register (WRLR) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
Command Lock Register In

SI 2Ch 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

High-Z MSB
SO

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

62
 MX25L12872F

9-31-2. Solid Protection Bits

The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.

When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.

The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.

Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.

Table 14. SPB Register

Bit Description Bit Status Default Type
00h = Unprotect Sector / Block
7 to 0 SPB (Solid Protection Bit) 00h Non-volatile
FFh = Protect Sector / Block

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

63
 MX25L12872F

Figure 60. Read SPB Status (RDSPB) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK
Mode 0
Command 32-Bit Address
(Note)

SI E2h A31 A30 A2 A1 A0

MSB
Data Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

Note: A31-A24 are don't care.

Figure 61. SPB Erase (ESSPB) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7
SCLK
Mode 0
Command

SI E4h

High-Z
SO

Figure 62. SPB Program (WRSPB) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39
SCLK
Mode 0
Command 32-Bit Address
(Note)

SI E3h A31 A30 A2 A1 A0

MSB

Note: A31-A24 are don't care

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

64
 MX25L12872F

9-31-3. Dynamic Protection Bits

The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enabling or disabling write-protection
to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each
64KB block in the rest of the memory. The DBPs can enable write-protection on a sector or block regardless of the
state of the corresponding SPB. However, the DPB bits can only unprotect sectors or blocks whose SPB bits are “0”
(unprotected).

When a DPB is “1”, the associated sector or block will be write-protected, preventing any program or erase
operation on the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”, the
associated sector or block will be unprotected if the corresponding SPB is also “0”.

DPB bits can be individually set to “1” or “0” by the WRDPB command. The DBP bits can also be globally cleared to
“0” with the GBULK command or globally set to “1” with the GBLK command. A WREN command must be executed
to set the WEL bit before sending the WRDPB, GBULK, or GBLK command.

The RDDPB command reads the status of the DPB of a sector or block. The RDDPB command returns 00h if the
DPB is “0”, indicating write-protection is disabled. The RDDPB command returns FFh if the DPB is “1”, indicating
write-protection is enabled.

Table 15. DPB Register

Bit Description Bit Status Default Type
00h = Unprotect Sector / Block
7 to 0 DPB (Dynamic Protection Bit) FFh Volatile
FFh = Protect Sector / Block

Figure 63. Read DPB Register (RDDPB) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK
Mode 0
Command 32-Bit Address
(Note)

SI E0h A31 A30 A2 A1 A0

MSB
Data Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

Note: A31-A24 are don't care.

Figure 64. Write DPB Register (WRDPB) Sequence

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK
Mode 0
Command 32-Bit Address Data Byte 1
(Note)

SI E1h A31 A30 A2 A1 A0 7 6 5 4 3 2 1 0

MSB MSB

Note: A31-A24 are don't care.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021
65
 MX25L12872F

9-31-4. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set
or clear all DPB bits at once.

The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.

The GBLK and GBULK commands are accepted in both SPI and QPI mode.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

9-31-5. Sector Protection States Summary Table

Protection Status Sector/Block

DPB SPB Protection State
0 0 Unprotected
0 1 Protected
1 0 Protected
1 1 Protected

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

66
 MX25L12872F

9-32. Program/Erase Suspend/Resume

The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations.

After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode
through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 12. Security Register Definition")

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

9-33. Erase Suspend

Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode,
the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation.
Reading the sector or Block being erase suspended is invalid.

After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including:
03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h,
00h, 35h, F5h, 15h, 2Dh, E2h, E0h)

If the system issues an Erase Suspend command after the sector erase operation has already begun, the device
will not enter Erase-Suspended mode until tESL time has elapsed.

Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state
of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is
cleared to "0" after erase operation resumes.

9-34. Program Suspend

Program suspend allows the interruption of all program operations. After the device has entered Program-
Suspended mode, the system can read any sector(s) or Block(s) except those be­ing programmed by the suspended
program operation. Reading the sector or Block being program suspended is invalid.

After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h,
66h, 99h, 00h, 35h, F5h, 15h, 2Dh, E2h, E0h)

Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the
state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB
is cleared to "0" after program operation resumes.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

67
 MX25L12872F

Figure 65. Suspend to Read Latency

tPSL / tESL
Suspend Command Read Command
CS#

tPSL: Program Latency

tESL: Erase Latency

Figure 66. Resume to Read Latency

tSE / tBE / tPP

Resume Command Read Command
CS#

Figure 67. Resume to Suspend Latency

tPRS / tERS
Resume Command Suspend Command
CS#

tPRS: Program Resume to another Suspend

tERS: Erase Resume to another Suspend

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

68
 MX25L12872F

9-35. Write-Resume

The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in
Status register will be changed back to “0”.

The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive
CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed
or not. The user may also wait the time lag of tSE, tBE, tPP for Sector-erase, Block-erase or Page-programming.
WREN (command "06h") is not required to issue before resume. Resume to another suspend operation requires
latency time of 1ms.

Please note that, if "performance enhance mode" is executed during suspend operation, the device can not
be resumed. To restart the write command, disable the "performance enhance mode" is required. After the
"performance enhance mode" is disabled, the write-resume command is effective.

9-36. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.

Both SPI (8 clocks) and QPI (2 clocks) command cycles can be accepted by this instruction. The SIO[3:1] are don't
care during SPI mode.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to "Table 16. Reset Timing-(Reset
Recovery time)" for tREADY2.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

69
 MX25L12872F

Figure 68. Software Reset Recovery

Stand-by Mode

CS# 66 99

tREADY2
Mode

Note: Refer to "Table 16. Reset Timing-(Reset Recovery time)" for tREADY2.

Figure 69. Reset Sequence (SPI mode)

tSHSL

CS#

Mode 3 Mode 3

SCLK Mode 0 Mode 0

Command Command

SIO0 66h 99h

Figure 70. Reset Sequence (QPI mode)

tSHSL

CS#

MODE 3 MODE 3 MODE 3

SCLK
MODE 0 MODE 0 MODE 0
Command Command

SIO[3:0] 66h 99h

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

70
 MX25L12872F

9-38. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.

The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.

SFDP is a JEDEC Standard, JESD216B.

For SFDP register values detail, please contact local Macronix sales channel for Application Note.

Figure 71. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24 BIT ADDRESS

SI 5Ah 23 22 21 3 2 1 0

High-Z
SO

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Dummy Cycle

SI 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

71
 MX25L12872F

10. RESET

After reset cycle, the device is in the following states:

- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

Table 16. Reset Timing-(Reset Recovery time)

Symbol Parameter Min. Typ. Max. Unit
Reset Recovery time (During instruction decoding) 40 us
Reset Recovery time (for read operation) 35 us
Reset Recovery time (for program operation) 310 us
tREADY2 Reset Recovery time(for SE4KB operation) 12 ms
Reset Recovery time (for BE64K/BE32KB operation) 25 ms
Reset Recovery time (for Chip Erase operation) 100 ms
Reset Recovery time (for WRSR operation) 40 ms

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

72
 MX25L12872F

11. POWER-ON STATE

The device is in the states below when power-up:

- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level

Please refer to the "Figure 79. Power-up Timing".

Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

73
 MX25L12872F

12. ELECTRICAL SPECIFICATIONS

Table 17. ABSOLUTE MAXIMUM RATINGS

RATING VALUE
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to VCC+0.5V
Applied Output Voltage -0.5V to VCC+0.5V
VCC to Ground Potential -0.5V to 4.0V

NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please
refer to Figure 72 and Figure 73.

Figure 72. Maximum Negative Overshoot Waveform Figure 73. Maximum Positive Overshoot Waveform

20ns 20ns 20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc
20ns
20ns 20ns

Table 18. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter Min. Typ. Max. Unit Conditions

CIN Input Capacitance 6 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

74
 MX25L12872F

Figure 74. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing reference level Output timing reference level

0.8VCC
0.7VCC AC
Measurement 0.5VCC
0.8V Level
0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 75. OUTPUT LOADING

DEVICE UNDER 25K ohm

+3.0V
TEST

CL
25K ohm

CL=30pF Including jig capacitance

Figure 76. SCLK TIMING DEFINITION

tCLCH tCHCL
VIH (Min.)
0.5VCC
VIL (Max.)
tCH tCL

1/fSCLK

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

75
 MX25L12872F

Table 19. DC CHARACTERISTICS

(Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V)

Symbol Parameter Notes Min. Typ. Max. Units Test Conditions

VCC = VCC Max,
ILI Input Load Current 1 ±2 uA
VIN = VCC or GND
VCC = VCC Max,
ILO Output Leakage Current 1 ±2 uA
VOUT = VCC or GND
VIN = VCC or GND,
ISB1 VCC Standby Current 1 10 50 uA
CS# = VCC
Deep Power-down VIN = VCC or GND,
ISB2 2 20 uA
Current CS# = VCC

f=133MHz, (4 x I/O read)

25 mA SCLK=0.1VCC/0.9VCC,
SO=Open

f=104MHz, (4 x I/O read)

ICC1 VCC Read 1 14 20 mA SCLK=0.1VCC/0.9VCC,
SO=Open

f=84MHz,
15 mA SCLK=0.1VCC/0.9VCC,
SO=Open

VCC Program Current Program in Progress,

ICC2 1 14 20 mA
(PP) CS# = VCC
VCC Write Status Program status register in
ICC3 10 12 mA
Register (WRSR) Current progress, CS#=VCC
VCC Sector/Block (32K,
Erase in Progress,
ICC4 64K) Erase Current 1 14 25 mA
CS#=VCC
(SE/BE/BE32K)
VCC Chip Erase Current Erase in Progress,
ICC5 1 14 25 mA
(CE) CS#=VCC
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.2 V IOL = 100uA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

76
 MX25L12872F

Table 20. AC CHARACTERISTICS

(Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V)
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC Clock Frequency for all commands (except Read) D.C. 133 MHz
fRSCLK fR Clock Frequency for READ instructions 50 MHz
fT Clock Frequency for 2READ/DREAD instructions Please refer to "Table 10. Dummy MHz
fTSCLK
fQ Clock Frequency for 4READ/QREAD instructions Cycle and Frequency Table (MHz)" MHz
Others > 66MHz 45% x (1/fSCLK) ns
tCH(1) tCLH Clock High Time (fSCLK) ≤ 66MHz 7 ns
Normal Read (fRSCLK) 7 ns
Others > 66MHz 45% x (1/fSCLK) ns
tCL(1) tCLL Clock Low Time (fSCLK) ≤ 66MHz 7 ns
Normal Read (fRSCLK) 7 ns
tCLCH(3) Clock Rise Time (peak to peak) 0.1 V/ns
tCHCL(3) Clock Fall Time (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 3 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 3 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 2 ns
tCHSH CS# Active Hold Time (relative to SCLK) 3 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 3 ns
From Read to next Read 7 ns
tSHSL tCSH CS# Deselect Time From Write/Erase/Program
30 ns
to Read Status Register
tSHQZ(3) tDIS Output Disable Time 8 ns
Clock Low to Output Valid Loading: 30pF 8 ns
tCLQV tV
Loading: 30pF/15pF Loading: 15pF 6 ns
Loading: 30pF 1 ns
tCLQX tHO Output Hold Time
Loading: 15pF 1 ns
tDP(3) CS# High to Deep Power-down Mode 10 us
(3) CS# High to Standby Mode without Electronic Signature
tRES1 30 us
Read
CS# High to Standby Mode with Electronic Signature
tRES2(3) 30 us
Read
tW Write Status/Configuration Register Cycle Time 40 ms
tBP Byte-Program 16 40 us
tPP Page Program Cycle Time 0.33 1.2 ms
tSE Sector Erase Cycle Time 25 120 ms
tBE32 Block Erase (32KB) Cycle Time 140 650 ms
tBE Block Erase (64KB) Cycle Time 250 650 ms
tCE Chip Erase Cycle Time 26 60 s
tESL(5) Erase Suspend Latency 25 us
tPSL(5) Program Suspend Latency 25 us
tPRS(6) Latency between Program Resume and next Suspend 0.3 100 us
tERS(7) Latency between Erase Resume and next Suspend 0.3 400 us

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

77
 MX25L12872F

Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. The value guaranteed by characterization, not 100% tested in production.
4. Test condition is shown as "Figure 74. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and "Figure 75.
OUTPUT LOADING".
5. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
6. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
7. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a pe-
riod equal to or longer than the typical timing is required in order for the erase operation to make progress.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

78
 MX25L12872F

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in "Figure 77. AC Timing at Device Power-Up" and "Figure 78. Power-Down Sequence" are for the sup-
ply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the
device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 77. AC Timing at Device Power-Up

VCC(min)
VCC
GND tVR tSHSL

CS#
tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL

tCHDX tCLCH

SI MSB IN LSB IN

High Impedance
SO

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 500000 us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 17. AC CHARACTERISTICS.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

79
 MX25L12872F

Figure 78. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 79. Power-up Timing

VCC
VCC(max)

Chip Selection is Not Allowed

VCC(min)

tVSL Device is fully accessible

VWI

time

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

80
 MX25L12872F

Figure 80. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 80. Power Up/Down and Voltage Drop" and "Table 21. Power-Up/Down
Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

tVSL Full Device

Access
Allowed

VPWD (max.)

tPWD

Time

Table 21. Power-Up/Down Voltage and Timing

Symbol Parameter Min. Max. Unit
tVSL VCC(min.) to device operation 800 us
VWI Write Inhibit Voltage 1.5 2.5 V
VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.9 V
tPWD The minimum duration for ensuring initialization will occur 300 us
VCC VCC Power Supply 2.7 3.6 V
Note: These parameters are characterized only.

13-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 40h (all Status Register bits are 0 except QE bit: QE=1).

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

81
 MX25L12872F

14. ERASE AND PROGRAMMING PERFORMANCE

Parameter Min. Typ. (1) Max. (2) Unit
Write Status Register Cycle Time 40 ms
Sector Erase Cycle Time (4KB) 25 120 ms
Block Erase Cycle Time (32KB) 0.14 0.65 s
Block Erase Cycle Time (64KB) 0.25 0.65 s
Chip Erase Cycle Time 26 60 s
Byte Program Time (via page program command) 16 40 us
Page Program Time 0.33 1.2 ms
Erase/Program Cycle 100,000 cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 2.7V, highest operation temperature, post program/erase cycling.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.

15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode)

Parameter Min. Typ. Max. Unit
Sector Erase Cycle Time (4KB) 15 ms
Block Erase Cycle Time (32KB) 100 ms
Block Erase Cycle Time (64KB) 200 ms
Chip Erase Cycle Time 25 s
Page Program Time 0.33 ms
Erase/Program Cycle 50 cycles
Notice:
1. Factory Mode must be operated in 20°C to 45°C and VCC 3.0V-3.6V.
2. In Factory mode, the Erase/Program operation should not exceed 50 cycles, and "ERASE AND PROGRAMMING
PERFORMANCE" 100k cycles will not be affected.
3. During factory mode, Suspend command (75h or B0h) cannot be executed.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

82
 MX25L12872F

16. DATA RETENTION

Parameter Condition Min. Max. Unit
Data retention 55˚C 20 years

17. LATCH-UP CHARACTERISTICS

Min. Max.
Input Voltage with respect to GND on all power pins 1.5 VCCmax
Input Current on all non-power pins -100mA +100mA
Test conditions: VCC = VCCmax, one pin at a time (compliant to JEDEC JESD78 standard).

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

83
 MX25L12872F

18. ORDERING INFORMATION

Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO. TEMPERATURE PACKAGE Remark

MX25L12872FM2I-10G -40°C to 85°C 8-SOP (200mil) Support Factory Mode

MX25L12872FZNI-10G -40°C to 85°C 8-WSON (6x5mm) Support Factory Mode

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

84
 MX25L12872F

19. PART NAME DESCRIPTION

MX 25 L 12872F M2 I 10 G
OPTION:
G: RoHS Compliant & Halogen-free

SPEED:
10: 104MHz

TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)

PACKAGE:
M2: 8-SOP (200mil)
ZN: 8-WSON (6x5mm)

DENSITY & MODE:

12872F: 128Mb

TYPE:
L: 3V

DEVICE:
25: Serial NOR Flash

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

85
 MX25L12872F

20. PACKAGE INFORMATION

20-1. 8-pins SOP (200mil)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

86
 MX25L12872F

20-2. 8-land WSON (6x5mm)

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

87
 MX25L12872F

21. REVISION HISTORY

Revision Descriptions Page

September 07, 2017
0.00 1. Initial Release. All

October 17, 2017 1. Removed document status "Advanced Information". All

1.0 2. Added 8-land WSON (6X5mm) package informaion. P4, 6, 84-85, 87
3. Updated Program and Erase values. P77, 82
4. Added WRSCUR and RDSCUR command figures. P55-56
5. Content modifications. P5, 34, 44, 84

April 09, 2021

1.1 1. Added "Support Performance Enhance Mode - XIP(execute-in-place)" P4,44
2. Modified "LATCH-UP CHARACTERISTICS" table P83
3. Added "Macronix Proprietary" footnote. ALL
4. Revised Doc. Title of package outline P86
5. Clarified single, dual, and quad I/O mode supporting in QE bit setting P30
descriptions.
6. Corrected "Read Electronic Signature (RES) Sequence" figures. P22-23
7. Corrected the Data Byte information of WRSCUR & WRSPB. P16
8. Added Output Driver Strength percentage information. P32
9. Modified the note descriptions for fTSCLK. P77-78
10. Content modification P1, 4, 10, 12-
13, 15, 16, 18,
20-22, 25, 33,
36-40, 42-43,
47-51, 53, 58-
59, 72, 75, 81
11. Modified the notes of ERASE AND PROGRAMMING PERFORMANCE P82
Table.

P/N: PM2541 Macronix Proprietary Rev. 1.1, April 09, 2021

88
 MX25L12872F

Except for customized products which have been expressly identified in the applicable agreement, Macronix's prod-
ucts are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household
applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury,
or severe property damages. In the event Macronix products are used in contradicted to their target usage above,
the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance
with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released
from any and all liability arisen therefrom.

Copyright© Macronix International Co., Ltd. 2017-2021. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix
NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO,
Macronix vEE, RichBook, Rich TV, OctaBus, FitCAM, ArmorFlash, LybraFlash. The names and brands of third
party referred thereto (if any) are for identification purposes only.

For the contact and order information, please visit Macronix’s Web site at: [Link]

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

89