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Lecture 06,07 cmos fabrication
(1) The document describes the basic fabrication process for CMOS integrated circuits. (2) It involves creating n-well regions for pMOS transistors on a p-type substrate, then depositing and patterning layers like gate oxide, polysilicon, n-type and p-type diffusions, contacts and metal to form the transistors, wires and connections. (3) The process uses photolithography and multiple masks to pattern each layer and allow selective etching and doping, building up the circuit layer-by-layer from the substrate up.
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Lecture 06,07 cmos fabrication
- 1. Dr. S.Meenatchi Sundaram,Department of Instrumentation & Control Engineering, MIT, Manipal ICE 4010: MICRO ELECTRO MECHANICAL SYSTEMS (MEMS) Lecture #06, 07 CMOS Fabrication Dr. S. Meenatchi Sundaram Email: [email protected] 1
- 2. Inverter Cross-section withWell and Substrate taps 2 • Typically use p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection • Use heavily doped well and substrate contacts / taps Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n+ p substrate p+ n well A Y GND VDD n+p+ substrate tap well tap n+ p+ VDD A=0 Y=1 GND OFF ON
- 3. Flow Diagram 3Dr S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Create n-Well regions and Channel Stops region Grow Field Oxide and Gate Oxide Deposit and pattern Polysilicon Layer Implant sources, drain regions and substrate contacts Create contact Windows, deposit and pattern metal layer
- 4. Fabrication Procedure –Basic Steps 4 • Masks: Each processing steps in the fabrication procedure requires to define certain area on the chip. This is known as Masks. • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain – Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design rules • The ICs are viewed as a set of pattern layers of doped Silicon, Polysilicon, Metal and Insulating Silicon Dioxide. • A layer must be Patterned before the next layer of material is applied on the chip. Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
- 5. Inverter Mask Set 5 •Transistors and wires are defined by masks • Cross-section taken along dashed line Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
- 6. Detailed Mask Views 6 •Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
- 7. Fabrication Steps 7 • Startwith blank wafer • Build inverter from the bottom up • First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate
- 8. Oxidation 8 • Grow SiO2on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate SiO2
- 9. Photoresist 9 • Used forlithography. • Lithography is a process used to transfer a pattern to layer on the chip. Similar to printing process. • Spin on photoresist (about 1 mm thickness) – Photoresist is a light-sensitive organic polymer – Positive Photoresist: Softens where exposed to light – Negative Photoresist: Harden where exposed to light, Not used in practice generally. Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate SiO2 Photoresist
- 10. Lithography 10 • Expose photoresistthrough n-well mask • Strip off exposed photoresist Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate SiO2 Photoresist
- 11. Etch 11 • Etch oxidewith hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate SiO2 Photoresist
- 12. Strip Photoresist 12 • Stripoff remaining photoresist – Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate SiO2
- 13. Inverter Cross-section 13 • Typicallyuse p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
- 14. Fabrication Procedure 14 • Well –Requires to build both pMOS and nMOS on single wafer. – To accommodate both pMOS and nMOS devices, special regions must be created in which the semiconductor type is opposite of the substrate type. – Also Known as Tubs. – Twin-tubs Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
- 15. n Well 15 • n-wellis formed with diffusion or ion implantation • Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si • Ion Implantation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n well SiO2
- 16. Strip Oxide 16 • Stripoff the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate n well
- 17. Polysilicon 17 • Deposit verythin layer of gate oxide – < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Thin gate oxide Polysilicon p substrate n well
- 18. Polysilicon Patterning 18 • Usesame lithography process to pattern polysilicon Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Polysilicon p substrate Thin gate oxide Polysilicon n well
- 19. n Diffusion 19 • Useoxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p substrate n well
- 20. n Diffusion 20 • Patternoxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n+ Diffusion p substrate n well
- 21. n Diffusion 21 • Historicallydopants were diffused • Usually ion implantation today • But regions are still called diffusion Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n well p substrate n+n+ n+
- 22. n Diffusion 22 • Stripoff oxide to complete patterning step Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal n well p substrate n+n+ n+
- 23. p Diffusion 23 • Similarset of steps form p+ diffusion regions for pMOS source and drain and substrate contact Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal p+ Diffusion p substrate n well n+n+ n+p+p+p+
- 24. Contacts 24 • Now weneed to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Contact p substrate Thick field oxide n well n+n+ n+p+p+p+
- 25. Metalization 25 • Sputter onaluminium over whole wafer • Pattern to remove excess metal, leaving wires Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Metal p substrate Metal Thick field oxide n well n+n+ n+p+p+p+
- 26. 3D and 2DView 26Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
- 27. Testing 27Dr S. MeenatchiSundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Defective IC Individual integrated circuits are tested to distinguish good die from bad ones.
- 28. Die cut andassembly 28Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Good chips are attached to a lead frame package.
- 29. Die Attach andWire Bonding 29Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal lead frame gold wire bonding pad connecting pin
- 30. Final Test 30Dr S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal Chips are electrically tested under varying environmental conditions.