FPGA board constraints

This repository provides constraint definitions in a standardised and distributed format, for decoupling board details from design sources.

Name	Name	Last commit message	Last commit date
Latest commit umarcor Jan 24, 2023 cd6ebf2 · Jan 24, 2023 History 125 Commits
.github/workflows	.github/workflows	ci/doc: update actions/checkout to v3	Nov 23, 2022
board	board	boards: add openFPGA	Nov 24, 2022
device/ICE40-UP5K	device/ICE40-UP5K	reorganise: board, device, flash, sdram and template	Jan 21, 2021
doc	doc	doc/conf: update extlinks syntax	Jan 24, 2023
.btd.yml	.btd.yml	doc: convert asciidoctor to Sphinx; use BTD	Dec 25, 2021
.gitignore	.gitignore	gitignore: update	Jan 18, 2022
LICENSE	LICENSE	initial commit	Oct 7, 2020
README.md	README.md	readme: update shield syntax (badges/shields#8671 )	Jan 24, 2023
constraints.drawio	constraints.drawio	readme: add img	Nov 23, 2022
constraints.py	constraints.py	add getConstraintFiles to the utility script	Jan 11, 2022
pyproject.toml	pyproject.toml	add pyproject.toml	Jan 7, 2022
requirements.txt	requirements.txt	add requirements.txt	May 16, 2022

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